Are there any known issues with [KL26] SPI using default setting of clock phase (CPHA == 0)?

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Are there any known issues with [KL26] SPI using default setting of clock phase (CPHA == 0)?

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jvasil
Contributor III

We're using SPI to communicate between two KL26 microcontrollers.  The slave device is set to use DMA and master is not.  Encountered problems that *seem* to be related to the clock phase.  At least the problem goes away when CPHA is set to 1 instead of 0.  I'd appreciate any references to issues trying to exchange data this way with CPHA set to 0.  I'm mostly trying to make sure that this fix isn't masking some problem that will pop up at some later date.  Thanks!

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jvasil
Contributor III

Further investigation showed that the problem we encountered was a coupling between the clock phase setting and the configuration of how the select line works.  After other developers found and fixed this problem, I finally found this reference to the issue buried in a reference manual:

  • “When C1[CPHA] = 1, the slave's SS input is not required to go to its inactive high level between transfers. In this clock format, a back-to-back transmission can occur” [p. 704 of KL26 Reference Manual]
  • “When C1[CPHA] = 0, the slave's SS input must go to its inactive high level between transfers.” [p. 706 of KL26 Reference Manual]

Perhaps a future version of Processor Expert could make suggestions about how SS should be configured based on how CPHA is set.  Even having this in the help text would be useful!

I'll also note that this special "rule" may only apply when the transmitter is using DMA.

Finally, I also saw somewhere (and I really don't know where) the erroneous statement that if the SSI clock polarity and phase were set the same on the transmitter and receiver, then the connection should work.  Clearly, this is not completely true since if CPHA is set to the default value of 0, and DMA is being used, the SS must go inactive between transfers.

Hopefully, this will help someone else in the future!!

Regards,
James

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jvasil
Contributor III

Further investigation showed that the problem we encountered was a coupling between the clock phase setting and the configuration of how the select line works.  After other developers found and fixed this problem, I finally found this reference to the issue buried in a reference manual:

  • “When C1[CPHA] = 1, the slave's SS input is not required to go to its inactive high level between transfers. In this clock format, a back-to-back transmission can occur” [p. 704 of KL26 Reference Manual]
  • “When C1[CPHA] = 0, the slave's SS input must go to its inactive high level between transfers.” [p. 706 of KL26 Reference Manual]

Perhaps a future version of Processor Expert could make suggestions about how SS should be configured based on how CPHA is set.  Even having this in the help text would be useful!

I'll also note that this special "rule" may only apply when the transmitter is using DMA.

Finally, I also saw somewhere (and I really don't know where) the erroneous statement that if the SSI clock polarity and phase were set the same on the transmitter and receiver, then the connection should work.  Clearly, this is not completely true since if CPHA is set to the default value of 0, and DMA is being used, the SS must go inactive between transfers.

Hopefully, this will help someone else in the future!!

Regards,
James

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adriancano
NXP Employee
NXP Employee

Hi,

Sometime I have seen that the problems with the phase, this is when enabling the CPOL or CPHA bits are solved enabling the Drive Strength of the IO port for output

I hope this information can help you.

Regards,

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi James,

Thank you very much for your focus on Freescale Kinetis product. I'm glad to provide service for you.

I've no idea to provide any suggestions for you since I was not very clearly with your issue.

So could you describe what exactly issue you encounted?

I'm looking forward to your reply.
Have a great day,

Ping

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