Are Kinetis IC's senstive to blowing up?

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Are Kinetis IC's senstive to blowing up?

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Contributor V

Hi --

I am designing a product with a K60DX256VLL10  processor in the 100 pin LQFP package.  Of the first 5 chips, four stopped working soon after installation, but I wrote it off to problems with the rest of the circuit.  I solved those problems, but the K60's keep dying.  The last two have dead shorts, power to ground, from installation.  On the most recent board, I tested the bare board, and the resistance from 3.3V to ground was infinite.  I installed only the processor, the JTAG connector, and two wires to a holder for two AA batteries.  As soon as I applied power, I could smell hot batteries, so I shut it off, removed the batteries, and tested the board.  Dead short.  I measured the continuity between each pair of pins on the K60.  None were shorted on the pins.  Power and ground were shorted, but not by solder.

I use a Metcal soldering iron, with a grounded tip (measured 0.6 ohms from tip to "green wire" ground). I am very careful about grounding, and not touching the IC.  I've been doing this work for quite a few years, and have not had this much trouble before.

Oddly enough, the fifth IC in that first batch of five I mentioned above has been running for about three months.  The ADCs are not reading accurately, but they are still running, and the rest of the IC is fine.

I still have three ICs that I have not taken out of the sealed strip that they came on.  Is there a way to get them tested?  Can I send the bad ones someplace to see what happened to them?  If not, are there tests I can run?

Gary Olmstead

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Senior Contributor II

Hi GaryOlmstead‌,

There are a number of things in this post that I would consider problematic for the proper operation of the Kinetis specifically and for 3.3V CMOS chips in general.  

What is the part number you're using for the power supply?  I don't think I've ever seen the noise you're describing on a Switch Mode Power Supply or a charge pump supply.  If you have a 600mV P-P pulses, you are at the datasheet maximum of 3.6 but I would definitely consider what you're describing as having a very high potential for damaging the chip.  If the components are within .250" and 0804 then I wouldn't think you'd have problems - there's something else going on here.  See my comment about power and ground planes below.  

I think you're expecting that the abuse you could put on old 5V bipolar TTL parts through in terms of power supply noise, fluctuations and out of spec operation will not affect modern CMOS logic.  Even something like a 5.0V NMOS 8051 or PICmicro would have difficulty surviving what you're putting into the MK60.  I don't think a AVR would handle this at all.  Regardless, for modern 32bit processors, you have to be pretty fastidious about power: but that's not that difficult or expensive to achieve.  

What do you mean "power and ground are mostly on internal layers" - do you not have a single layer for each of these?  How are you connecting/stitching between the power and ground areas?  Nothing succeeds like a full PCB plane taken up by ground, followed by Vdd - if you don't know what you're doing you could have induced currents and voltages in what should be constant voltage rails.  

You haven't mentioned decoupling on the chip - I recommend that you follow what's done on the Freedom/Tower board as a reference.  That includes common mode chokes on Vdd and Vss.  

Internal clocking should be okay but not if you're going to use USB or E'net in your application. 

There MUST be a pull up (100k is fine) on the reset line and I would recommend a power line monitor to make sure reset is pulled low if the voltage gets below a certain point (I use 3.15V) as it provides a hysteresis delay between power good and reset high.  I believe (and the NXP engineers can confirm) that not pulling up the reset line during power up will kill the chip (and, I believe will produce the hard short that you are experiencing) - I know it will on other chips.  

The "soft" Zener is especially worrisome, if you see 4.0V on a Kinetis pin, then chances are you'll kill the chip (or any 3.3V part).  The 4.0V is 'way outside of operating spec and appears to be sourcing more than 100mA of current (or else the internal pin diodes would pull the voltage down to 3.3V) which is more than the part can sink.  This will definitely kill the chip.  

I'm still happy to look at your schematic but I recommend you find somebody with experience with 3.3V CMOS logic to redo your PCB layout so that you have a guide for the future.  

Sorry for being blunt.  

myke

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Senior Contributor II

Hey GaryOlmstead‌,

I have not seen anything close to what you're seeing - I've personally soldered many (dozens) Kinetis parts to and from boards (as well as having my local board stuffer do it) without any issues.  

The Kinetis parts are as robust as anything I've ever worked with.  

It sounds like your manual rework processes are good, but I have to question the electrical design and PCB layout.  In the Kinetis K60 ADC readings ar way off thread, you said that "there's an issue with the power supply board layout, and power is very noisy" - you've never said how noisy and I'm wondering if the chips have been damaged because of overvoltage conditions.  Along with that, I suspect that your experiment, with just power and a programming connector, some necessary signals were not connected causing the internal short to form.  

I've learned that when working with any MCU/Processor you need to have:

  • Power
  • Clocks
  • Reset

right before you can expect your application to work.  

You've had a frustrating experience and I would be happy to look at your schematics (just as relates to the K60 if you are concerned about IP) as well as the PCB layout - as I'm sure other people here would be as well.  

I suspect that a second set of eyes on your design will find an issue in your design/wirring that you have missed or not considered significant.  

myke

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Contributor V

Hi Myke --

The power supply problem consists of bursts of noise at the frequency of the power supply, 500 KHz.  Each burst is two cycles of 600 mV p-p at 120MHz, followed by about four cycles of the same frequency but not more than 100 mV p-p.  It then dies down to nothing until the next pulse.  I have an eval board for that IC,  and it doesn't have that problem.  I copied all of the circuit and most of the board layout, but the eval board uses 0402 components, while I used 0805 because they are easier to handle.  Mine are less than a quarter of an inch farther away, but that is too much.  Lesson learned, I won't cut that corner again.  Unfortunately, this is a four layer board, with power and ground are mostly on internal layers.  There are some places I can make existing parts larger, or different, or both.  I will try that later today.

Do you think that 600 mV p-p is too much for the Kinetis?  Back in the days of 5V parts, they were guaranteed to stand up to 7V, so 600 mV was not good, but not fatal.  I know that 3.3V parts are much less forgiving.  What do you think?

I am relying on the internal clock and reset circuit.  Was that a mistake?

There is one spot in the design where a part at 12V feeds signal into a 10K series resistor, 3.3V zener and then directly into the K60.  The zener seems to be rather soft, I have seen 4V on that pin.  Is that too much for the Kinetis?

Thanks for the offer to look at my schematic.  The IP on this project is all software, there's nothing valuable in the hardware.  If none of the above provides an "Ah ha!" moment, I will send it along.

Gary

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Senior Contributor II

Hi GaryOlmstead‌,

There are a number of things in this post that I would consider problematic for the proper operation of the Kinetis specifically and for 3.3V CMOS chips in general.  

What is the part number you're using for the power supply?  I don't think I've ever seen the noise you're describing on a Switch Mode Power Supply or a charge pump supply.  If you have a 600mV P-P pulses, you are at the datasheet maximum of 3.6 but I would definitely consider what you're describing as having a very high potential for damaging the chip.  If the components are within .250" and 0804 then I wouldn't think you'd have problems - there's something else going on here.  See my comment about power and ground planes below.  

I think you're expecting that the abuse you could put on old 5V bipolar TTL parts through in terms of power supply noise, fluctuations and out of spec operation will not affect modern CMOS logic.  Even something like a 5.0V NMOS 8051 or PICmicro would have difficulty surviving what you're putting into the MK60.  I don't think a AVR would handle this at all.  Regardless, for modern 32bit processors, you have to be pretty fastidious about power: but that's not that difficult or expensive to achieve.  

What do you mean "power and ground are mostly on internal layers" - do you not have a single layer for each of these?  How are you connecting/stitching between the power and ground areas?  Nothing succeeds like a full PCB plane taken up by ground, followed by Vdd - if you don't know what you're doing you could have induced currents and voltages in what should be constant voltage rails.  

You haven't mentioned decoupling on the chip - I recommend that you follow what's done on the Freedom/Tower board as a reference.  That includes common mode chokes on Vdd and Vss.  

Internal clocking should be okay but not if you're going to use USB or E'net in your application. 

There MUST be a pull up (100k is fine) on the reset line and I would recommend a power line monitor to make sure reset is pulled low if the voltage gets below a certain point (I use 3.15V) as it provides a hysteresis delay between power good and reset high.  I believe (and the NXP engineers can confirm) that not pulling up the reset line during power up will kill the chip (and, I believe will produce the hard short that you are experiencing) - I know it will on other chips.  

The "soft" Zener is especially worrisome, if you see 4.0V on a Kinetis pin, then chances are you'll kill the chip (or any 3.3V part).  The 4.0V is 'way outside of operating spec and appears to be sourcing more than 100mA of current (or else the internal pin diodes would pull the voltage down to 3.3V) which is more than the part can sink.  This will definitely kill the chip.  

I'm still happy to look at your schematic but I recommend you find somebody with experience with 3.3V CMOS logic to redo your PCB layout so that you have a guide for the future.  

Sorry for being blunt.  

myke

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Contributor V

Hi Myke --

I should have been clearer.  I copied the K60 Tower board schematic for bypass caps, but for some reason didn't use the inductors, I don't know why not.  The Tower card has a pull-up resistor on reset, but no reset module.  The resistor is buried in a remote corner of a different page from the processor, and I just missed it.  I will figure out how to mount one.

Ground occupies one entire (internal) layer.  All the digital parts are together, and their 3.3V is on one (internal) layer.  All the analog parts are together, and their power is physically separate, but on the same layer as the digital power.

The switcher is a Maxim MAX17504.  The output has noise of a similar shape, but an order of magnitude lower.  Adding capacitors doesn't fix it.  I will talk to Maxim.

I have already added a Schottky buffer, powered from 3.3V, between the zener and the K60.  The input circuit is my client's pet design, they claim it works perfectly with their previous processor (Raspberry Pi at 5V), but I haven't seen any proof of it.  I know I am just moving the problem back one step, but the inverter is easier to swap out than the K60.  I considered an opto-coupler, and will probably go with that next time, but their circuit can't drive one, so for this board, an inverter will have to do.  I've hated this circuit from day 1 for several reasons, but I don't have any way to field test a replacement to prove that mine is better.  Their working environment can be very noisy, electrically.

I'll hold off sending a schematic for now.  I have lots to do here.

Thanks for your help.  I really appreciate it.


Gary

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