2 PWM signals, phase time detection of 10ns granularity

[christophevigny]

I'm trying to select the correct hardware (Kinetis or other if not possible) that will enable us to detect the phase time we have between 2 PWM signals inputs.

The minimum phase time detection we need to detect is 10ns.

I've checked several datasheets for the k20's, k50's but I have some trouble understanding the General switching specs.

What solution would you recommend?

[xiangjun_rong]

If the minimum phase time is 10nS, if you fill the 10nS with 5 ticks, the tick frequency will reach up to 500MHz, the frequency is beyond the scope of timer input frequency.

Let me list the Timer maximum input clock frequency:

MC56F84xxx: 100MHz

Cold Fire family has the similar parameter, it is about 80 or 100MHz.

If you want to detect the phase shift, the timer has to have capture function, which means that both rising/falling edge of tested signal can trigger an capture interrupt, the speed of the core to handle the ISR is another problem.

In  conclusion, I have not found the processor which can measure 10ns pulse width.

But the unique feature of the eFlexPWM module can test the deadtime tenure of PWM signal with the unused PWM pins(the unused PWM pins can be configured as input mode), the PWM resolution is about 10ns for MC56F84xxx family, but the deadtime must have several PWM clocks. The MC56F847xx and MPC56xx all have eFlexPWM module.

pls go to the website to download RM of MC56F84xxx:

http://tinyurl.com/nssr28o

[christophevigny]

We only need to detect the phase time between the signals raising edges.

1 tick in 10ns is enough. If our 2 signals have a phaseshift < 10ns we do not need to detect it. On the other hand if >10ns we must detect it. So if I follow your reasonning a 100Mhz timer on the GPIO could do the trick. But still have my doubts. The rough idea I have is to have a main loop counting only if (PWM_1_STATE != PWM_2_STATE ) and have those PWM_X_STATE flag values changed only on raising edge interrupts.

The problem is that the ISR time activation is quite long (~16ns in best case, no worst case value) and even with a 100Mhz I have no guaranty that my 2 ISR will trigger with a constant time after the real rising edges (afraid of going beyond 20-30ns).

If you sense any false idea in my reflection please let me know.

Could you tell me what would be the minimum detectable phase time between 2 signals with a k20 120MHz? (specs says GPIO on 60Mhz timer). I don't know how to determine it.

Thx.

[Hui_Ma · Accepted solution]

K20 120MHz product FlexTimer module provides input capture function. The FlexTimer module refer clock is bus clock, which could up to 75MHz. When FTM channel works as input capture, the CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on the channel input. The FlexTimer module input capture sample clock is bus clock divided by 4. That means the input capture frequency should below 18.75MHz. The Minimum detected phase time is 54ns.

Wish it helps.

Best regards,

Ma Hui

[christophevigny]

It helps in my comprehension, thank you. Could you tell me within the kinetis family which could be the best candidate to minimize the phase time detection?

Regards.

[Hui_Ma]

So far, Kinetis Max. core clock frequency is 150MHz and bus clock frequency is 75MHz. The 54ns phase time detection is the minimum time Kinetis could support.

Thank you for the attention.