关于K64中的SPI的非FIFO的使用(disable FIFO of SPI slave)

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关于K64中的SPI的非FIFO的使用(disable FIFO of SPI slave)

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yuanhanchen
Contributor III

我在使用非FIFO的时候,遇到了这样一个问题:就是在仿真的时候,从机接收中断函数打断点,查看在read POPR寄存器后,RX FIFO就会载入下一个数据,而非是空的,在测试之后我有一个猜想:因为在使用单步执行时,从执行read POPR命令后到下一句之间的时间被拉长了,长到这个时间足够主机传来的数据被RX FIFO接收(夸张的说,如果时钟够快,在正常接收到数据之前的时间段上打断点,在执行到这个断点时,查看RX FIFO都会显示有下一帧的数据,因为在遇到断点停止的一刹那,就已经有足够的时间使得数据被接收到) ,所以在下一句的时候,寄存器会出现的现象是:RX FIFO并没有空,而是保存了下一帧的数据。

大家可以讨论下是不是这个原因。

Eng:

I was in the use of non-FIFO, encountered such a problem: the simulation time, receives from the interrupt function break point, after viewing read POPR register, RX FIFO will load the next data, not empty and after the test I have a guess: because the use of single-step, from the command to execute read POPR a time between being stretched under a long enough time to the data from the host is received RX FIFO (exaggeration to say that, if the clock is fast enough, in normal reception of the break point in time before the data segment in the implementation of the breakpoint to view the RX FIFO data will show the next frame, since the breakpoint is encountered stop the moment, we have enough time so that the data is received), so the next one when the register phenomenon occurs is: RX FIFO did not have time, but save the data for the next frame.

We can discuss the next is not the reason.

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Hui_Ma
NXP TechSupport
NXP TechSupport

正如我之前说的,SPI在debug模式下并未停止工作,而是在继续收发数据。这样虽然Debug调试窗口程序看起来停住了,但是SPI通信仍然在进行(可用示波器进行观察)。在SPI初始化阶段,将SPIx_MCR[FRZ]位置位,这样单步调试就应该不会产生你说描述的现象。

祝顺利。

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

The SPI module provides the Debug mode with below description:

pastedImage_0.png

It need to check  SPIx_MCR[FRZ] bit. As reference manual shows, if this bit is cleared, the SPI slave communication normally without debugger affection.


Wish it helps.

Have a great day,
Ma Hui
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yuanhanchen
Contributor III

Hi,

I see the next register, this value is set by default I did not change it, I think it is the time when debugging causes. What do you think?

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

Which register? SPIx_TCR?


Wish it helps.

Have a great day,
Ma Hui
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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yuanhanchen
Contributor III

Sorry my English is not very good, I mean SPIx_MCR [FRZ] is the default. This problem is due to my single-step run time is greater than the first trigger an interrupt to trigger the second time of the interruption.

抱歉我的英语不是很好,我的意思是SPIx_MCR[FRZ]是默认值。这个问题的出现是由于我单步运行的时间大于第一次触发中断到第二次触发中断的时间。

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444 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

正如我之前说的,SPI在debug模式下并未停止工作,而是在继续收发数据。这样虽然Debug调试窗口程序看起来停住了,但是SPI通信仍然在进行(可用示波器进行观察)。在SPI初始化阶段,将SPIx_MCR[FRZ]位置位,这样单步调试就应该不会产生你说描述的现象。

祝顺利。

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yuanhanchen
Contributor III

谢谢你的帮助,我会置位MCR[FRZ]测试下,顺便说下,还是中文用起来舒服。。。。:smileyhappy:

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