Hi,
we can use FEI mode to generate 24M bus clock.
with 37.5khz internal clock, ICSOUT can generate 48Mhz output. ICSOUT=37.5k*1280=48Mhz
according to below clock diagram, we can set DIV1 as 1 to divide ICSOUT by 2, thus generated system/core clock is 48/2=24Mhz
thus we can set SIM_CLKDIV=0x11100000.
with above code, system/core clock is 48/2=24Mhz, bus clock=48/2/2=12Mhz. I made a demo under KDS3.0. see attached.
can this help you?
Have a great day,
Jennie Zhang
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Hi Vignesh,
in my first response, I set system/core clock by setting DIV1 in SIM module
your code sets system/core clock by setting BDIV in ICS module.
Carlos is correct, you can only remove ICS_C3= 0x90; to get 24M core clock if don't consider clock Trim.
with your code, in FEI mode, FLL output 37.5k*1280=48Mhz
with this code:
ICS_C2|=ICS_C2_BDIV(1) ; // BDIV=divide by 2
ICSOUTCLK = FLL output/2 = 48/2=24Mhz
thus with default SIM_CLKDIV value: DIV1=00, we can get system/core clock = ICSOUTCLK = 24Mhz
can this help you?
Have a great day,
Jennie Zhang
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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That means you ran the bus clock at 48 Mhz as mine and the MCU did not find any problem.I ran my MCU in debug mode with Segger(internally SWD).Did you run this at the same way.
