Clock source (FIRC) frequency used is 48Mhz.
For ADC having a sampling rate of 1Khz, what will the conversion clock cycles to be configured (INPSAMP)
Based on your configuration with a 6 MHz ADC clock and the maximum allowed input sampling time (INPSAMP = 255
), the minimum achievable ADC conversion frequency is approximately 19.35 kHz.
Pay attention to RM, section 60.3.18 Conversion time
But I want the sampling rate to be 1Khz, so how can I configure this in terms of clock cycles
So you mean actually triggering rate. I have somehow expected continuous conversions, but you may trigger ADC conversion 1000x per second thus you have conversion rate 1kS/sec.
It is indeed not set by INPSAMP, but it is just application dependent. INPSAMP says how many clocks sampling phase takes.