I2C Slave Sleep Requirements

[jaredm]

I am evaluating the K32L2B series microcontrollers for a new product.

The product requirements specify the microcontroller remain in sleep most of the time, but can be woken up by the I2C Slave peripheral. The I2C bus speed is always 400kbps.

When I2C is active, RUN mode is required to support 400kbps (per RM, VLPS only supports 100kbps).

When the system sleeping, VLPS is the preferred mode. According to the RM, I2C will support "static, address match wakeup" in VLPS mode.

Does "address match wakeup" work at 400kbps when in VLPS mode?

[jaredm · Accepted solution]

Testing has demonstrated that address match wakeup works at 400kbps in VLPS mode. The datasheet implies that the address match wakeup logic is independent of the normal slave receive logic. During address match wakeup the address bits are clocked in only using SCL, whereas normal slave receive uses the configured baud rate to sample and perform bit granularity clock stretching (if enabled).