Customer may want to debug FRDM-IMX93 with the SWD interface of Jtag. This doc give an introduction about how to do that.
Hardware: FRDM-IMX93,J-link.
1.Rework FRDM-IMX93 board and get the VREF(1.8V) from TP707 for SWD, show as the following picture.
2. Remove the R3017 and R3018 in the following picture.
3.Connect FRDM-IMX93 and PC through J-link as the following pictures.
4.Switch the sw1 to 1001 to the serial download of the M33, then run the J-link commander.
The command is as following:
J-Link>device MIMX9352_M33
J-Link>speed 4000
Selecting 4000 kHz as target interface speed
J-Link>si swd
Selecting SWD as current target interface.
J-Link>power on
J-Link>connect
The full log is as following:
SEGGER J-Link Commander V8.10 (Compiled Sep 26 2024 08:38:41)
DLL version V8.10, compiled Sep 26 2024 08:37:48
Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Jan 30 2023 11:28:07
Hardware version: V10.10
J-Link uptime (since boot): N/A (Not supported by this model)
S/N: 600109556
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=1.800V
Type "connect" to establish a target connection, '?' for help
J-Link>device MIMX9352_M33
J-Link>speed 4000
Selecting 4000 kHz as target interface speed
J-Link>si swd
Selecting SWD as current target interface.
J-Link>power on
J-Link>connect
Device "MIMX9352_M33" selected.
Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 12us
InitTarget() start
InitTarget() end - Took 2.53ms
Found SW-DP with ID 0x5BA02477
DPIDR: 0x5BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[1]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[3]: Core found
AP[3]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x411FD210. Implementer code: 0x41 (ARM)
Feature set: Mainline
Cache: No cache
Found Cortex-M33 r1p0, Little endian.
Cortex-M (ARMv8-M and later): The connected J-Link (S/N 600109556) uses an old firmware module that does not handle I/D-cache correctly. Proper debugging functionality cannot be guaranteed if cache is enabled
FPUnit: 8 code (BP) slots and 0 literal slots
Security extension: implemented
Secure debug: enabled
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
[0][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
[0][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
[0][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
[0][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
[0][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
Memory zones:
Zone: "Default" Description: Default access mode
Cortex-M33 identified.
J-Link>
5.You can also switch the sw1 to 0011 boot the A55 and stop at U-boot, then run the J-link commander
The following is the command:
J-Link>device MIMX9352_M33
J-Link>speed 4000
Selecting 4000 kHz as target interface speed
J-Link>si swd
Selecting SWD as current target interface.
J-Link>power on
J-Link>connect
The following is the full log:
SEGGER J-Link Commander V8.10 (Compiled Sep 26 2024 08:38:41)
DLL version V8.10, compiled Sep 26 2024 08:37:48
Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Jan 30 2023 11:28:07
Hardware version: V10.10
J-Link uptime (since boot): N/A (Not supported by this model)
S/N: 600109556
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=1.806V
Type "connect" to establish a target connection, '?' for help
J-Link>device MIMX9352_M33
J-Link>speed 4000
Selecting 4000 kHz as target interface speed
J-Link>si swd
Selecting SWD as current target interface.
J-Link>power on
J-Link>connect
Device "MIMX9352_M33" selected.
Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 27us
InitTarget() start
InitTarget() end - Took 3.89ms
Found SW-DP with ID 0x5BA02477
DPIDR: 0x5BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[1]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[3]: Core found
AP[3]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x411FD210. Implementer code: 0x41 (ARM)
Feature set: Mainline
Cache: No cache
Found Cortex-M33 r1p0, Little endian.
Cortex-M (ARMv8-M and later): The connected J-Link (S/N 600109556) uses an old firmware module that does not handle I/D-cache correctly. Proper debugging functionality cannot be guaranteed if cache is enabled
FPUnit: 8 code (BP) slots and 0 literal slots
Security extension: implemented
Secure debug: enabled
CoreSight components:
ROMTbl[0] @ E00FF000
[0][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
[0][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
[0][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
[0][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
[0][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
[0][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
Memory zones:
Zone: "Default" Description: Default access mode
Cortex-M33 identified.
J-Link>device MIMX9352_A55_0
Disconnecting from J-Link...O.K.
Device "MIMX9352_A55_0" selected.
Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end - Took 19us
Found SW-DP with ID 0x5BA02477
DPIDR: 0x5BA02477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)
AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
Using preconfigured AP[1] as APB-AP
AP[1]: APB-AP found
DebugRegs + CTI manually specified. ROM table scan skipped.
Cortex-A55 @ 0x80810000 (configured)
CoreCTI @ 0x80820000 (configured)
Debug architecture: ARMv8.2
6 code breakpoints, 4 data breakpoints
Processor features:
EL0 support: AArch64 + AArch32
EL1 support: AArch64 + AArch32
EL2 support: AArch64 + AArch32
EL3 support: AArch64 + AArch32
FPU support: Single + Double + Conversion + single arithmetic
ARMv8-A/R: The connected J-Link (S/N 600109556) uses an old firmware module V0 with known problems / limitations.
Add. info (CPU temp. halted)
Current exception level: EL2
Exception level AArch usage:
EL0: AArch32
EL1: AArch32
EL2: AArch64
EL3: AArch64
Non-secure status: Non-secure
Cache info:
Inner cache boundary: none
LoU Uniprocessor: 0
LoC: 0
LoU Inner Shareable: 0
VMSAv8-64: Supports 48-bit VAs
Memory zones:
Zone: "Default" Description: Default access mode
Zone: "AP0" Description: MEM-AP (AHB-AP)
Zone: "AP1" Description: MEM-AP (APB-AP)
Zone: "AP3" Description: MEM-AP (AHB-AP)
Cortex-A55 identified.
Memory zones:
Zone: "Default" Description: Default access mode
Zone: "AP0" Description: MEM-AP (AHB-AP)
Zone: "AP1" Description: MEM-AP (APB-AP)
Zone: "AP3" Description: MEM-AP (AHB-AP)
J-Link>
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