Switching from external to internal clock on MC56F82748

[JPE]

Hi there!

We are using an external 8 MHz crystal as the clock source on in of our designs with the MC56F82748 and are now facing some issues where the DSC stops executing its code completely.
The clock generator then uses the PLL to increase the core frequency to 100 MHz and the "HS frequency" to 200 MHz.

We are suspecting some noise issues on the clock signal and would like to switch over to the "internal relaxation oscillator" as the clock source to figure out, if this removes the issue.

For the switching of the clock source I have tried to follow the instructions in chapter 18 of the "MC56F827xx Reference Manual" by executing the following instructions:

1. Switch "Clock Source" from "PLL output divided by 2" to "MSTR_OSC" by clearing the ZSRC (Clock Source) bit in the OCCS_CTRL register
2. Switch "Prescaler Clock" from "External reference" to "8 MHz relaxation oscillator" by setting both PRECS-bits (Prescaler Clock Select) to 0.
3. Switch back "Clock Source" from "MSTR_OSC" to "PLL output divided by 2" by setting the ZSRC (Clock Source) bit in the OCCS_CTRL register
   In between these instructions I have added some dummy instructions to add some delay.

After this sequence, the timers in the DSC are running at 1/25 of the clock frequency while using the external crystal.
This is the ratio between the 8 MHz clock source and the 200 MHz "HS" output of the PLL, so one explanation could be, that the clock source is still the "MSTR_OSC" instead of the PLL.

But then of course the question is, what is wrong with my command sequence to switch the clock source from external to internal reference?

[JPE]

Hi XiangJun,

thanks for your response.
However, what you suggest is exactly what I'm doing.
The PLL is already set up to generate 200 MHz before the switch, as the external crystal also runs on 8 MHz just as the internal relaxation oscillator, so I'm not even changing the postscaler or the divider of the PLL.
I'm also checking the LCK1-bit in the OCCS_STAT-register before switching from MSTR_OSC to the PLL clock source.

So what else could be wrong in case the CPU keeps on running on the MSTR_OSC frequency?

BR. Jörn

[xiangjun_rong]

Hi,

Unfortunately, the MC56F827xx does not have a block diagram for the clock.

I copied a block diagram from MC56F825x, but the PLL output clock frequency is not the same.

When you use PLL, you have to switch the MSTR_OSC clock, then configure PLL so that it can output 200MHz, and check if it is locked. After it is locked, switch to Fpll/2 clock source.

Hope it can help you

BR

XiangJun Rong

[JPE]

Hello again,

OK, I found the reason for my problem.

I am using the two definitions "OCCS_MSTR_OSC_OUTPUT" and "OCCS_PLL_OSC_OUTPUT" from the "occs.h"-file to select the prescaler clock.
After checking with the reference manual I realized, that the values for those definitions are switched and therefore I was actually selecting the MSTR_OSC instead of the PLL output in my code.

After fixing this mistake in the header file the switching from external to internal clock works fine.

BR. Jörn

[xiangjun_rong]

Hi,

Pls download SDK package from the link:

https://mcuxpresso.nxp.com/en/welcome

The example code use the internal 8MHz IRC and PLL to get 200MHz for the PLL output.

I copy the code, pls have a try.

BR

XiangJun Rong

/*
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* Clock initialization functions.
*/

/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v8.0
processor: MC56F82748
package_id: MC56F82748VLH
mcu_data: ksdk2_0
processor_version: 0.10.5
board: TWR-MC56F8200
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

#include "fsl_clock.h"
#include "clock_config.h"

/*******************************************************************************
* Definitions
******************************************************************************/

/*******************************************************************************
* Variables
******************************************************************************/

/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}

/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: BUS_2X_CLK.outFreq, value: 100 MHz}
- {id: BUS_CLK.outFreq, value: 50 MHz}
- {id: CPU_CLK.outFreq, value: 50 MHz}
- {id: IIC0_FLT_CLK.outFreq, value: 50 MHz}
- {id: MSTR_OSC.outFreq, value: 8 MHz}
- {id: PWM_2X_CLK.outFreq, value: 200 MHz}
- {id: PWM_CLK.outFreq, value: 100 MHz}
- {id: ROSC200kHz_CLK.outFreq, value: 200 kHz}
- {id: ROSC8MHz_CLK.outFreq, value: 8 MHz}
- {id: SCI0_CLK.outFreq, value: 50 MHz}
- {id: SCI1_CLK.outFreq, value: 50 MHz}
- {id: SYS_2X_CLK.outFreq, value: 100 MHz}
- {id: SYS_CLK.outFreq, value: 50 MHz}
- {id: SYS_FTFA.outFreq, value: 25 MHz}
- {id: TMR_CLK.outFreq, value: 50 MHz}
settings:
- {id: OCCS.COD.scale, value: '2', locked: true}
- {id: OCCS.DIV.scale, value: '1', locked: true}
- {id: OCCS.EXT_SEL.sel, value: OCCS.OSC}
- {id: OCCS.PLLDB.scale, value: '50', locked: true}
- {id: OCCS.PWM_DIV2.sel, value: OCCS.PLL_DIV2}
- {id: OCCS.ZSRC.sel, value: OCCS.PLL_DIV2}
- {id: OCCS_CTRL_PLLPD_CFG, value: Enabled}
- {id: OCCS_OSCTL2_ROPD200K_CFG, value: Enabled}
sources:
- {id: OCCS.ROSC200kHz.outFreq, value: 200 kHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
clock_config_t occsConfig_BOARD_BootClockRUN =
{
.bCrystalOscEnable = false, /* Crystal oscillator is disabled */
.bFircEnable = true, /* RC oscillator 8 MHz is enabled */
.bSircEnable = true, /* RC oscillator 200 kHz is enabled */
.bPllEnable = true, /* PLL is enabled */
.bCrystalOscMonitorEnable = false, /* External crystal (XOSC) clock monitor is disabled. */
.eFircSel = kCLOCK_FircSel_8M, /* FIRC normal mode, output 8M */
.eCrystalOscMode = kCLOCK_CrystalOscModeFSP,/* High power mode of the external oscillator (crystal oscillator in in Full Swing Pierce (FSP) mode) */
.eExtClksrc=kCLOCK_ExtClkSrcCrystalOsc, /* External crystal oscillator (OSC) */
.eClkInSel = kCLOCK_SelClkIn0, /* External reference clock CLKIN0 */
.eMstrOscClksrc=kCLOCK_MstrOscClkSrcFirc,/* 8 MHz / 400KHz fast internal RC oscillator */
.eMstr2xClksrc=kCLOCK_Mstr2xClkSrcPllDiv2,/* PLL output clock divided by 2 */
.eMstr2xClkPostScale = kCLOCK_PostscaleDiv2,/* mast_2x_clk = clkSrc / 2 */
.u32PllClkFreq = 400000000U, /* PLL output frequency: 400000000Hz */
};

/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Check the run mode - switch all power regulators in the normal mode if they are placed in standby or disabled mode. */
/* If the advanced power mode is enabled in the Flash Options register. */
if (FTFA->FOPT & 0x1) {
/* If the Very Low Power Run mode is active. */
if (SIM->PWRMODE & SIM_PWRMODE_VLPMS_MASK) {
SIM->PWRMODE &= ~SIM_PWRMODE_VLPMODE_MASK;
while (SIM->PWRMODE & SIM_PWRMODE_VLPMS_MASK){} /* Waiting to switch back from the Very Low Power Run mode. */
}
/* If the Low Power Run mode is active. */
if (SIM->PWRMODE & SIM_PWRMODE_LPMS_MASK) {
SIM->PWRMODE &= ~SIM_PWRMODE_LPMODE_MASK;
while (SIM->PWRMODE & SIM_PWRMODE_LPMS_MASK) {} /* Waiting to switch back from the Low Power Run mode. */
}
while (!(PMC->STS & PMC_STS_SR27_MASK)) {} /* Waiting for small regulator 2.7V supply is ready to be used. */
} else {
/* If a standby or power down state of any regulator is activated. */
if (SIM->PWR & (SIM_PWR_SR12STDBY_MASK | SIM_PWR_SR27PDN_MASK | SIM_PWR_SR27STDBY_MASK | SIM_PWR_LRSTDBY_MASK)) {
SIM->PWR = 0; /* Enter the run mode - switch all power regulators into the normal mode. */
while (!(PMC->STS & PMC_STS_SR27_MASK)) {} /* Waiting for small regulator 2.7V supply is ready to be used. */
}
}
/* Set clock configuration of the OCCS module. */
CLOCK_SetClkConfig(&occsConfig_BOARD_BootClockRUN);
}