Hi, Ivan,
Regarding your question how the phase-shift funmction of PWM is implemented, this is the basic theory.
As you know that the eFlexPWM module has 4 sub-module: SM0, SM1, SM2 and SM3, each sub-module SMn can generates two PWM signal:PWM_SMnA and PWM_SMnB, the two signals PWM_SMnA and PWM_SMnB can be independent or complementary with deadtime insertion.
The PWM sub-module works independently, from theory, each PWM sub-module is a counter, it can count tick from PWMA_SMnINIT to PWMA_SMnVAL1, then from PWMA_SMnINIT to PWMA_SMnVAL1 repeatedly. When the counter reach up to PWMA_SMnVAL3, PWM_SMnA signal becomes High logic, when the counter reach up to PWMA_SMnVAL4, PWM_SMnA signal becomes Low logic, so that the PWM cycle time is PWMA_SMnVAL1-PWMA_SMnINIT. The PWM duty cycle time is PWMA_SMnVAL4-PWMA_SMnVAL3.
If you want to implement phase-shift feature while the SMn works in complementary mode, as the example, you can use SM0 and SM1, of course, the SM0 and SM1 module must be synchronized by setting the PWMA_SM0CTRL2[INIT_SEL]=00,PWMA_SM1CTRL2[INIT_SEL]=10.
This is the register setting for the the SM0 and SM1:
PWMA_SM0INIT=PWMA_SM1INIT=-2000;
PWMA_SM0VAL1=PWMA_SM1VAL1=2000; //the duty cycle=4000 tick
SM0:
PWMA_SM0VAL3=-2000;
PWMA_SM0VAL4=0; //the PWMA_SM0A duty cycle is 2000/4000=50%
The SM0 register setting is fixed.
SM1:
PWMA_SM1VAL3=-2000;
PWMA_SM1VAL4=0; //the PWMA_SM0A duty cycle is 2000/4000=50%
Result: the PWMA_SM1A and PWMA_SM0A signal are the same
PWMA_SM1VAL3=-1000;
PWMA_SM1VAL4=-1000+2000=1000; //the PWMA_SM0A duty cycle is 2000/4000=50%
Result: the PWMA_SM1A lag behind PWMA_SM0A signal 90 degree
PWMA_SM1VAL3=0;
PWMA_SM1VAL4=0+2000=2000; //the PWMA_SM0A duty cycle is 2000/4000=50%
Result: the PWMA_SM1A lag behind PWMA_SM0A signal 180 degree, in other words, they are inverter.
This is the code to update the phase shift in reload ISR.
Hope it can help you
BR
Xiangjun rong
void PWMA_0_Reload_ISR(void)
{
PWMA_REGS_ALL *ptr = &udtPWMAreg;
//GPIOE_DR &= ~GPIOE_DR_D_3;
setReg16Bits(PWMA_SM0STS,0x1000); /* Clear interrupt request flag */
invertReg16Bits(GPIOF_DR,0x040); /* Toggle GPIOF6 output LED8 */
ptr->SM1.pwmsmval2 = (Word16)ptr->SM1.pwmsmval2 + 2;
if((Word16)ptr->SM1.pwmsmval2>=0) //ptr->SM1.pwmsmval1)
{
ptr->SM1.pwmsmval2 = -2000; //ptr->SM1.pwmsminit;
}
ptr->SM1.pwmsmval3 = (Word16)ptr->SM1.pwmsmval2 + 2000;
phase = (ptr->SM1.pwmsmval2 - ptr->SM0.pwmsmval2);
FMSTR_Recorder();
PWM_A_Update(&udtPWMAreg);
}
