MC56F847X EEPROM maximum number of erasures cycles?

[IvyGuo]

When the Flexnvm  was partitioned as the EEPROM backup data memory，the eeprom can write about 1.6 millions cycles or not ？ How to set the FMC and FTFL to achive the goal？

In datasheet， there are some set of data show the write cycle of eeprom  up to 100M cycles. how to set the  EEPROM backup to FlexRAM ratio to 256 or 512?  Is there some registers to finish the setting?

[IvyGuo]

Thanks for your help,Lorenzo,xianjun：

your description “ if you select the minimum "simulated EEPROM" size you get a ratio of 32K/32 = 1024, that is about 5 milion writes using 16bit or 32bit writes or about 1.6 milion writes using 8bit writes.”  refer to this equation right？  sofrware use this api? 

DEFlashPartition(&ftfl_cfg, 0x36U, 0x02, FlashCommandSequence); //0x36: 256bytes EEPROM data size, 0x02: 16kbytes EEPROM buckup size

And another question is  this chip has a built in writeing balance strategy?  user mannul shows that the :

After a sector in EEPROM backup is full of EEPROM data records, EEPROM data

records from the sector holding the oldest data are gradually copied over to a previously

erased EEPROM backup sector. When the sector copy completes, the EEPROM backup

sector holding the oldest data is tagged for erase

[xiangjun_rong]

Hi,

1)refer to this equation right？ sofrware use this api? 

>>>>Yes, the ratio is the EEPROM backup size/EEPROM data size, for your case, it is 16kB/256B=62

2)And another question is this chip has a built in writeing balance strategy?

>>>>Yes, the The EEPROM file system  is smart enough, it's strategy is to use all backup FlexNVM rather than using a fixed part of flexNVM part.

Hope it can help you

BR

XiangJun Rong

[xiangjun_rong]

Hi,

Pls refer to the section 20.4.11.14 Program Partition Command, the FCCOB4[EEESIZE] bits defines the FlexRAM size when you use command 0x80 to execute EEPROM partition operation. The FlexNVM Partition Code defines the FLEX NVM size for the EEPROM function.

Hope it can help you

BR

XiangJun Rong

[Lorenzo_Mch_IT · Accepted solution]

See MC56F847xx Reference Manual, Rev. 2, 3/2014.

At page 422 there is the formula they used for "simulated EEPROM" write cycles estimation.
At page 423 there is a graph showing what to expect, but it's misleading because  projects the estimation beyound the available data flash.

With 32KB of data flash fully assigned as "EEPROM backup", if you select the minimum "simulated EEPROM" size you get a ratio of 32K/32 = 1024, that is about 5 milion writes using 16bit or 32bit writes or about 1.6 milion writes using 8bit writes.

If you have to use the maximum size for "simulated EEPROM" (2KB) the ratio goes down to 16, so you can expect about 60K of 16/32bit writes or about 25K of 8bit writes (assuming 10K writes for "normal" flash memory).

The registers with the settings for simulated EEPROM size and backup are described at page 404,405,406.

It's a bit tricky, because while the "simulated EEPROM" size is exactly the value written in the EEESIZE field (of Data flash IFR 0x00FD), the DEPART field (of Data Flash IFR 0x00FC) is NOT the "EEPROM backup" size, but instead the data flash size to NOT be allocated as eeprom backup.

So, to get 32KB all for EEPROM backup, set DEPART to  0011 binary or 1000 binary.