!In the LP Wait Mode, it says there that all peripheral modules are enabled, except NanoEdge and cyclic ADC’s. Is it also possible to configure the UART pin to change mode to be used as a GPIO during this mode of operation? If this is not possible, will the UART still operate in the same way that it does in normal run mode? Otherwise, what are some possible scenarios that could happen with the reduced clock frequency for the UART peripheral?
In line with the question above, what would be the maximum baud rate that can be
achieved when using LP mode in both the MC56F82723 and the MC56F847xx? As this is critical
to communication timings.
Going by the information provided in the RM, there is no constraint on part of SCI. You can enable the SCI in Wait mode also with a maximum frequency as good as your run mode. the only point to consider is whether the source clock is being changed while going from one power mode to the other and the other dividers. Care must be taken while going to LPWAIT and VLPWAIT as the constraints on maximum frequency would come up then.
You can as well configure SCI pins to work as GPIO just before entering the WAIT mode.