ADC Scan Control Register problem on MC56F84789

[marco76]

Hello,

I already wrote the question in the Codewarrior for MCU section ( ADC Scan Control Register problem on MC56F84789 ) but to now no one could help me!

If is it possible i rewrite here the problem.

We're using ADC12 in independet parallel triggerd mode.

We want to acquire 6 samples on ADCB triggered via PDB1 (4 sync) syncing with ADC12_SCTRL in one PWM 8Khz cycle. At the end of ADC scan we want to have ADC ISR

The configuration of PWM, PDB1, AOI are correct. We have checked disabling the ADC12_SCTRL register and we monitoring the event end of ACD scan with a oscciloscope (4 event)

According to PE configurations,  the samples  8~11 are got from ANB0.

Sample 8 -> ANB0 

Sample 9 -> ANB0

Sample 10 -> ANB0

Sample 11 -> ANB0

Sample 12 -> ANB2

Sample 13 -> ANB6

The PWM period is 125us

The PDB1 sync is set at 1us, 20us, 40us and 80us

Our intention is like below:

      PDB1 at 1us   ==> Sample 8 -> ANB0    ==> Halt

      PDB1 at 20us  ==> Sample 9 -> ANB0   ==>Halt

      PDB1 at 40us   ==>Sample 10 -> ANB0    ==>Halt

      PDB1 at 80us   ==> Sample 11 -> ANB0 / Sample 12 -> ANB2 / Sample 13 -> ANB6 ==> End (Intterrupt end of ADC scan)

We set the ADC work in independent triggered parallel mode. In source code, we configured ADC12_SCTRL as 0x00F0,  the ADCB should work as below:

      SC4  = 1 :  Sample 8  ==> Halt

      SC5 = 1 : Sample 9 ==> Halt

      SC6 =1 :  Sample 10 ==> Halt

      SC7 =1 :  Sample 11 ==> Halt

      SC12 = 0 : Sample 12 ==> Continue

      SC13 = 0 : Sample 13 ==> Continue

      SC14 = 0 : Sample 14 ==> Continue

      SC15 = 0 : Sample 15 ==> Continue

Unfortunately does not work!!!

The event end of ACD scan triggered every six synchronization hits of module PDB1 (monitored with oscilloscope). Then, the samples 11, 12, 13 are not acquired together as desired close to the last PDB1 synconization pulse.

We use the AN4608 and the AN4583 as reference. The difference in the application note AN4608  is that it 's used the scan control but in simultaneous parallel triggred mode.

UPDATE:

We try some change and we discover that if we change from independent mode to simultaneous mode all it works correctly!!!

As we desired the last three samples are acquired together at the last sync of PDB1 and than the event end of ACD scan triggered!!!

We believe that the problem is present only if the independent mode is set!!!

We think we are doing something wrong or there may be an error at microcontroller level!

Thanx for any help!

Marco

[johnlwinters · Accepted solution]

We have noted the issue you reported and revised the Reference Manual.

The use cases for the scan control have been restricted.

Please see the reference manuals at this location:

http://www.nxp.com/products/microcontrollers-and-processors/more-processors/dsp-dsc/dscs/mc56f84xxx/...#

[xiangjun_rong]

Hi, Marco,

firstly, pls check the ADC12_SDIS register, the corresponding sample bits should be cleared.

From theory, your solution is okay, for ADCB, the first three synchronizing signals trigger ADCB and samples sample[8], sample[9], sample[10] one by one, the last ONE synchronizing signal launches a scan mode and samples sample[11], sample[12], sample[13] continuously.

If the ADC12_SDIS register is set up correctly, I think it is a bug of the ADC hardware module. As a test of using ADCA, if you sample sample[0], sample[1], sample[2] with three synchronizing signals, then sample[4], sample[5], sample[6] with another ONE synchronizing signal, what is the result?

As a workaround, because "We try some change and we discover that if we change from independent mode to simultaneous mode all it works correctly!!!", for your application, the samples from ADCA module are usless, so in the ISR, you just pick up the samples from ADC_Resultx registers of ADCB, it is okay.

i have checked the errata, your issue is not mentioned.

BR

Xiangjun rong

[marco76]

Hi Xiangjun rong

The corresponding sample bits of ADC12_SDIS register are cleared.

The workaround for us is no good. We must use ADCA for other operation with a different timing and syncing.

I also checked the errata before write on the community forum. I believe that not many companies use ADC in this way and then perhaps not yet encountered this problem!

This is the code generated by PE unless the limiting high/low and offset register

void ADC12_Init(void)

{

  /* ADC12_SDIS: DS=0xC0F0 */

  setReg16(ADC12_SDIS, 0xC0F0U);       /* Set sample disable register */

  /* ADC12_CLIST1: SAMPLE3=5,SAMPLE2=4,SAMPLE1=2,SAMPLE0=0 */

  setReg16(ADC12_CLIST1, 0x5420U);     /* Set channel list register 1 */

  /* ADC12_CLIST3: SAMPLE11=8,SAMPLE10=8,SAMPLE9=8,SAMPLE8=8 */

  setReg16(ADC12_CLIST3, 0x8888U);     /* Set channel list register 3 */

  /* ADC12_CLIST4: SAMPLE15=0,SAMPLE14=0,SAMPLE13=0x0E,SAMPLE12=0x0A */

  setReg16(ADC12_CLIST4, 0xEAU);       /* Set channel list register 4 */

  /* ADC12_SCTRL: SC=0xF0 */

  setReg16(ADC12_SCTRL, 0xF0U);        /* Set scan control register */

  /* ADC12_SCHLTEN: SCHLTEN=0 */

  setReg16(ADC12_SCHLTEN, 0x00U);      /* Set scan halted interrupt enable register */

  /* ADC12_CAL: SEL_VREFH_B=0,SEL_VREFLO_B=0,SEL_VREFH_A=0,SEL_VREFLO_A=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  setReg16(ADC12_CAL, 0x00U);          /* Set AD calibration mode and references */

  /* ADC12_PWR2: ??=0,??=0,DIV1=9,??=0,??=0,??=0,??=0,SPEEDB=3,SPEEDA=3 */

  setReg16(ADC12_PWR2, 0x090FU);       /* Set Power 2 register */

  /* ADC12_CTRL3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMASRC=0,SCNT1=3,SCNT0=3 */

  setReg16(ADC12_CTRL3, 0x1BU);        /* Set control register 3 */

  /* ADC12_CTRL2: DMAEN1=0,STOP1=1,START1=0,SYNC1=1,EOSIE1=1,CHNCFG_H=0,SIMULT=0,DIV0=9 */

  setReg16(ADC12_CTRL2, 0x5809U);      /* Set control register 2 */

  /* ADC12_CTRL1: DMAEN0=0,STOP0=1,START0=0,SYNC0=1,EOSIE0=1,ZCIE=0,LLMTIE=0,HLMTIE=0,CHNCFG_L=0,??=0,SMODE=5 */

  setReg16(ADC12_CTRL1, 0x5805U);      /* Set control register 1 */

  /* ADC12_STAT: CIP0=0,CIP1=0,??=0,EOSI1=1,EOSI0=1,ZCI=0,LLMTI=0,HLMTI=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  setReg16(ADC12_STAT, 0x1800U);       /* Clear EOSI flag(s) */

  /* ADC12_HILIMSTAT: HLS=0xFFFF */

  setReg16(ADC12_HILIMSTAT, 0xFFFFU);  /* Clear limit status flags */

  /* ADC12_LOLIMSTAT: LLS=0xFFFF */

  setReg16(ADC12_LOLIMSTAT, 0xFFFFU);  /* Clear limit status flags */

  /* ADC12_ZXSTAT: ZCS=0xFFFF */

  setReg16(ADC12_ZXSTAT, 0xFFFFU);     /* Clear limit status flags */

  /* ADC12_PWR: ASB=0,??=0,??=0,??=0,PSTS1=0,PSTS0=0,PUDELAY=0x1A,APD=0,??=0,PD1=0,PD0=0 */

  setReg16(ADC12_PWR, 0x01A0U);        /* Set power control register */

}

[xiangjun_rong]

Hi, marco,

Thank you for the feedback. Can you help to develop a simple example which can duplicate the issue so that we can test on our tower board. If we confirm this is an issue, we will submit the issue to application&design team so that they can update in next errata and fix the bug in next version of processor.

Thanks

BR

Xiangjun Rong