32-bit compare with the Quad Timer

[jimcole]

I have Quad Timers 2&3 set up as a "Cascaded" down counter where timer 3's input is timer 2's output.  The main CNTR registers are connected internally. That part is working, but I'm not so sure that the rest of the registers are working as they should.  I'm trying to set up an interrupt when I get a 32-bit compare as well as when the (pair) of counters hit zero.  My code is rough, but at this point it looks like the compare registers are acting independently, not as a single 32-bit register because I'm getting interrupts much faster than I should.  When I set up interrupts in "Cascaded" mode which timer do I set up for interrupts?  Is it the low ordered one (timer 2) or the high ordered one (timer 3)?  Neither counter will be zero. It needs to be the logical AND of the two compare registers.  The Reference Manual has a really simple example of generating a 30 second interrupt that is no help.  Am I trying to do something that can even be done?

[xiangjun_rong]

Hi, Jim,

when you use Cascaded counter mode for T3, and T2 output is the tick for T3, the T3:T2 is NOT a standard 32bits single Timer, they are two independent timers, each works independently. When the T3 counter is equal to the compare register value of T3, the T3 will generate interrupt, at the instant, the T2 counter is the compare register value of T2.

There is not  way to trigger an interrupt by logical AND of the two compare registers, because  the T2 and T3 generate interrupt independently.

For your application, I suggest you have only T3 generate interrupt, I think the interrupt interval cycle time is compare_T3:compare_T2

Hope it can help you

BR

Xiangjun rong