Hi Tom and Fang,
many thanks for your help,
well, proceeding really slow due to family tasks, btw had a look on the quirks and i don't seems to see anything useful,
but will check better.
Also, i don't see anything directly related to this in the errata.
What is happening here is that, i send a ACMD51, and just after i get a DMA transfer completed succesfully (DINT bit only set, no errors), and this seems true, since reading the dma buffer i see always the same and correct data read (zeroed the buffer before).
Then, sdhci.c common the irq handler, before exiting, reads again the interrupt status register, in a loop, since the sdhci.c driver is organized to perform a loop in the irq, to check if some other events are happening. And in this second read of int status reg, a TC + DAT (data crc error) is reported.
It is like, after the proper DMA read, a transfer completed + error is reported. How does it work the DATA CRC check after a DMA read ? The controller inspects the dma buffer ?
Regards,
Angelo