Hi
The "bus clock" is in fact half the PLL clock.
The following is a define to calculate the PIT using a 1k prescaler (where REQUIRED_MS is the value in ms):
#define TICK_DIVIDE (((PLL_CLOCK/2/1048) + REQUIRED_MS/2)/REQUIRED_MS)
Regards
Mark
Hi
In the clock module the following are set:
- CCHR = 4 (divides the input frequency from 25MHz to 5MHz)
- SYNCR = 0x4007 (sets the PLL up to generate 60MHz internal clock)
Regards
Mark
Thanks.
PIT document referring Internel Bus clock below, Is Internal Bus clock is 60MHz (PLL Freq)?. I have 52233DEMO, on that board, there is one 25MHz crystal, to calculate modulus value, if I set PRE to 8 (1000), then what clock speed I have to assume?.
The PIT’s timeout value is given here:
1/(Internal Bus clock) * 2(Prescaler Value+1) * Module Value = Time (seg).
Hi
The "bus clock" is in fact half the PLL clock.
The following is a define to calculate the PIT using a 1k prescaler (where REQUIRED_MS is the value in ms):
#define TICK_DIVIDE (((PLL_CLOCK/2/1048) + REQUIRED_MS/2)/REQUIRED_MS)
Regards
Mark