V4 Coldfire and DS Data Strobe?  Motorola Bus Timing Change?

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V4 Coldfire and DS Data Strobe?  Motorola Bus Timing Change?

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stevejanisch
Contributor IV

I last used Motorola/Freescale processors back in the 68000 days.  Back in the day you used R/W (Read/Write) and DS (Data Strobe) signals to access the data bus.

 

I am now converting projects using that processor to a V4 MCF5441x.  I noticed that there is a R/W signal for the FlexBus, but there doesn't seem to be a functional equivalent to the DS data strobe.  Since I have existing IO boards that were using this signal, I suppose I will have to re-create it from the new signals.

 

But I was wondering if anyone knew the history of when Freescale made what looks like a philosophy change in bus access... is this following a new industry standard/specification or was it changed for some other reason?  As I recall there was a big debate between the Motorola vs Intel bus timing... it looks like this is yet a third approach.

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TomE
Specialist I

> Back in the day you used R/W (Read/Write) and DS (Data Strobe) signals to access the data bus.

Back in the 68000 day we had to decode the address bus ourselves to produce the chip selects. This was usually an "asynchronous" and glitchy decode, so AS and DS were needed to qualify when the decode was valid.

Ever since the 68300 series, the chips have provided decoded chip selects. Depending on your external boards, you may find you can tie your external DS and chip-select signals together.

If they're your own boards, you'll have to see what sort of signal timing they can handle to see what simplifications you can get away with.

Is this a VMEBus system? If it is then you'll have to guarantee that your new CPU board generates valid VMEBus signal timing, and that will probably take extra hardware. You'll need to drop the 60MHz FlexBus clock down as well.

> is this following a new industry standard/specification or was it changed for some other reason?

It is part of what got us from 8 MHz 68000 CPUs taking 4 (or was it 5?) clocks per fetch, read and write cycle to 3 GHz mainstream and 1.2GHz embedded CPUs issuing multiple instructions per clock.

Tom