Touble when more than 1 PIT is deployed (5282)

[SVC2]

Hi,

I have written a PIT0_init()  function that generates an ISR upon timeout.

I also have a PIT1_init()  function that generates an ISR upon timeout.

When I call PIT0_init () only within the application, everything works as expected (ISR called at regular interval).

Dido when I call PIT1_init() only within the application, everything works as expected.

Nevertheless, when I call both PIT0_init() and PIT1_init(), no ISR are generated anymore.

We can only use one PIT at a time?

Any hints?

S.

Code:

//FUNCT: Bsp_PIT_err_t PIT0_init (const uint32 timeout_ms){ return pit_init(timeout_ms, 0);}//FUNCT: Bsp_PIT_err_t PIT1_init (const uint32 timeout_ms){ return pit_init(timeout_ms, 1); }//FUNCT: static Bsp_PIT_err_t pit_init(const uint32 timeout_ms, const uint8 pit_num){ const uint16 PRESCALER=0;// [0; 2^16] const uint32 PMR = (timeout_ms * SYSTEM_CLOCK_KHZ/2)  - 1; // Modulo [0; 0xFFFF] uint8  isr_level  = ISR_LEVEL_PIT0; uint8  isr_priority=ISR_PRIORITY_PIT0; uint32 isr_mask   = MCF_INTC_IMRH_INT_MASK55; uint8  intC0_ICR  = 55;  // Make sure that number is 0, 1 and 2 if(pit_num !=0 && pit_num != 1 && pit_num != 2)  return BSP_PIT_WRONG_CHNL;  // Validate Modulo if(PMR > 0xFFFF)  return BSP_PIT_WRONG_MODULO;  // Point to right PIT if(pit_num==0) {  isr_level  = ISR_LEVEL_PIT0;  isr_priority=ISR_PRIORITY_PIT0;  isr_mask   = MCF_INTC_IMRH_INT_MASK55;  intC0_ICR  = 55; } if(pit_num==1) {  isr_level  = ISR_LEVEL_PIT1;  isr_priority=ISR_PRIORITY_PIT1;  isr_mask   = MCF_INTC_IMRH_INT_MASK56;  intC0_ICR  = 56; } if(pit_num==2) {  isr_level  = ISR_LEVEL_PIT2;  isr_priority=ISR_PRIORITY_PIT2;  isr_mask   = MCF_INTC_IMRH_INT_MASK57;  intC0_ICR  = 57; }     // Disable interrupts mcf5xxx_irq_disable ();   //  Sets the level and priority of this interrupt MCF_INTC0_ICR(intC0_ICR) |=  (MCF_INTC_ICR_IL(isr_level) | MCF_INTC_ICR_IP(isr_priority)); // Unmask interrupt source    MCF_INTC0_IMRH &= ~(isr_mask | MCF_INTC_IMRL_MASKALL) ;      // Configure PIT     // Set PRE (prescaler) MCF_PIT_PCSR(pit_num)  = (uint16)(MCF_PIT_PCSR_PRE(PRESCALER));          // Modulo count  MCF_PIT_PMR(pit_num) = (vuint16)(PMR & 0xFFFF);  // Pit Control Status Register MCF_PIT_PCSR(pit_num) |=  MCF_PIT_PCSR_OVW |      MCF_PIT_PCSR_PIE |  // Enable interrupt     MCF_PIT_PCSR_PIF |  // Reset PIF     MCF_PIT_PCSR_RLD |  // Copy Modulus in counter when 0 is reached     MCF_PIT_PCSR_EN;    // EN = 1     // Enable interrupts    mcf5xxx_irq_enable ();          // Done    return BSP_PIT_NO_ERROR;    }

[RichTestardi]

> MCF_INTC0_IMRH &= ~(isr_mask | MCF_INTC_IMRL_MASKALL) ;

One small thing I noticed is I don't think you want to use the IMRL's MASKALL on the IMRH...

But I doubt that could cause what you are seeing.

> MCF_INTC0_ICR(intC0_ICR) |=  (MCF_INTC_ICR_IL(isr_level) | MCF_INTC_ICR_IP(isr_priority));

I also don't think you want "|=" here...  Just "=".  (The reset value is 0, so you should be OK anyway.)

-- Rich