Reset value of D0

[J_rg]

Hi,

is there a list of possible values for D0 after reset? I can see
0xCF437013 on my MCF5474, but I can't find any explanation of the values. Is it possible to decode the mask revision of the processor?

Regards,
Jörg

[DrSeuss]

The Mask revision is located in the CIM it can be determined:

    switch ((MCF_CIM_CIR & 0xFFC0) >> 6)

Values are listed in the Ref Man.

The DO/D1 register out of reset contain ColdFire Core information.

Please see the mcf5xxx.c and mcf5xxx.h files in sample code on any ColdFire product page.

http://www.freescale.com/files/netcomm/software/app_software/code_examples/MCF5213SC.zip

[J_rg]

Thanks, however this information seems to be slightly inconsistent with my 5474. According to your .h it has no MMU, whereas I think it has.

The next is that I can't find a CIM_CIS register on the 5474. Are you sure that you don't refer me to the 5213?

Which RM do you refer to? I just rechecked the 5474RM and the CFv4eRM. No information about these bits...

Message Edited by J�rg on 05-11-200603:55 AM

[ricks]

Hi all,

I recently began looking at the d0 and d1 processor config registers also. You can find better documentation on these in the Coldfire Family Programmer's Reference Manual, Rev. 3, pages 1-21 to 1-26.

We run on a 5484. I also noticed (as cross-referenced by the information in the manual) that d0 claims we have no MMU, which is funny since we've been using it for months to kill outstanding xl bus transactions (another interesting problem all together).

I find the most useful information in these registers to be the processor revision, bits 16-19 in d0, as we are interested in the resolution of certain errata in subsequent steppings of the version 4.

~Rick

Message Edited by ricks on 05-11-200603:31 PM

[mnorman]

There is an error in the reset D0 values for all processors in the MCF547x/8x families.  All report that there is no MMU, but the MMU is present.  The remainder of the encodings correctly reflect the architecture of the families.

-MN