Reset on watch dog timer expires

[MCF52233]

Hi all,
I hv MCF52233DEMO board in which i want to use watch dog timer to reset the program after watch
dog timer expires.
/******* from main.c ********************/
MCF_INTC0_IMRL &= ~( MCF_INTC_IPRL_INT8 | 1 ); // Enable Irq 8 (bit 0 should allways be 0)

MCF_INTC0_ICR07=MCF_INTC_ICR_IL(4);

MCF_SCM_CWCR = MCF_SCM_CWCR_CWE | // Enable WDT
//MCF_SCM_CWCR_CWT(1) | // 2^19 bus cycles.
MCF_SCM_CWCR_CWT_2_23 |
MCF_SCM_CWCR_CWTA | // Enable Transfer Ack.
MCF_SCM_CWCR_CWTAVAL ;

/************** exception.c *************/

__interrupt__ void wdtISR( void )
{

MCF_SCM_CWCR |=MCF_SCM_CWCR_CWTAVAL |MCF_SCM_CWCR_CWTIF ;
MCF_RCM_RCR |= MCF_RCM_RCR_SOFTRST; // Set software reset request bit.
}

and also add entry in vetor table at 72 i.e. 64+8

but rather than program reset program stop executing.
Is i miss something or any flaw to set the values??
Plz help me out.

[terryt]

I'm running the InterNiche stack using the M52233Demo board also.

Same issue here. It doesn't work!!!!!!!!! 

/**Int_handlers.c **/

__interrupt__ void wdtISR( void )
{

MCF_SCM_CWCR |=MCF_SCM_CWCR_CWTAVAL |MCF_SCM_CWCR_CWTIF ;
MCF_RCM_RCR |= MCF_RCM_RCR_SOFTRST; // Set software reset request bit.
}

/**Int_handlers.c **/

MCF_INTC0_ICR07=MCF_INTC_ICR_IL(7); //highest priority.
 

MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK1); //Using one other Interrupt. 
MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK7); //Watchdog Interrupt. 


MCF_SCM_CWCR = MCF_SCM_CWCR_CWE | // Enable WDT
MCF_SCM_CWCR_CWT_2_23 |
MCF_SCM_CWCR_CWTA | // Enable Transfer Ack.
MCF_SCM_CWCR_CWTAVAL ;

/***MCF52235_vectors.s**

vector48   .long _wdtISR

It never causes an interrupt at this vector. 

The link says issued resolved. I say it isn't. Can anyone clear this up?

Thanks,

Terry

[MCF52233]

Hi terry,

just replace this line

MCF_INTC0_ICR07=MCF_INTC_ICR_IL(7); //highest priority.

to

MCF_INTC0_ICR08=MCF_INTC_ICR_IL(7); //highest priority.

[terryt]

Hey Abhijit,

Thanks for the quick reply. It gave me some focus on what to look for.

The only reference to Control registers concerning the Watchdog was the one below.  

It wasn't very clear in this data sheet. 

From the Data Sheet MCF52235RM.pdf Section 13-10..

CWRI

Core watchdog interrupt select.

0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is

programmed in the interrupt control register 7 (ICR7) of INTC0.

Same code from me before but I hardcoded the ICR08 = 0x3F;

Here is what worked for me.......

MCF_SCM_CWCR = MCF_SCM_CWCR_CWE

| // Enable WDT
MCF_SCM_CWCR_CWT_2_23 |
MCF_SCM_CWCR_CWTA | // Enable Transfer Ack.
MCF_SCM_CWCR_CWTAVAL ;

MCF_INTC0_ICR08 |= 0x3F; //highest priority. 

MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK8); //Watchdog Interrupt. 
 

[terryt]

I was trying to fix the last couple lines. I hit the tab key which sent before I wanted to.......

Here is a cleaned up version......... 

MCF_SCM_CWCR = MCF_SCM_CWCR_CWE

                          | MCF_SCM_CWCR_CWT_2_23

                          | MCF_SCM_CWCR_CWTA

                          | MCF_SCM_CWCR_CWTAVAL

                          | MCF_SCM_CWCR_CWTIF;

MCF_INTC0_ICR08 |= 0x3F; //highest priority. 

MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK8); //Watchdog Interrupt.

MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_MASKALL); //Enable.

Thanks again Abhijit.......

[MCF52233]

Hi terry,

    The configuration is looking fine but might be still remains something.

I'm not a expert but still i can give some ways to approch d task.

U can try without InterNiche.just create new project which include this

watch dog releted configuration.

Finally 1 question is remains dat how u test it???

In my case i made a basic timer who clear the releted register

MCF_SCM_CWSR = 0x55;
MCF_SCM_CWSR = 0xAA;

when i commented dat part i.e not clearing this then ISR is callled from vector48. 

[terryt]

Hey Abhijit,

What helped me out the most was using a baseline Processor Expert project with having only a watchdog (no Internice). This showed me the correct values for all registers and vectors. The datasheet was just not clear enough.

I tested by setting a breakpoint at the interrupt vector routine and not writing the 0x55 & 0xAA to the CWSR.

It took about 20 seconds for the interrupt to engage. It works!

Thanks again,

TT

[mjbcswitzerland · Accepted solution]

Hi

Here is code to configure a 2s watchdog timeout

CWCR = (CWE | WATCHDOG_2_SEC | CWTA | CWTAVA | CWTIF);

fnSetIntHandler(SW_WD_VECTOR, (unsigned char *)_sw_wdog_timeout);

IC_ICR_0_8 = (INTERRUPT_LEVEL_7 | INTERRUPT_PRIORITY_7);

IC_IMRL_0 &= ~(SW_WDG_PIF_INT_L | MASK_ALL_INT);

The handling routine is 

static __interrupt__ void _sw_wdog_timeout(void)
{
    RESET_RCR = SOFT_RST;                                                // command a soft reset of the board
}

Note that the watchdog should best be given highest (NMI) priority so that it can fire when another interrupt routine fail.

It is however not fool-proof since it relies on the watchdog interrupt handler being able to run (which is not 100% guarantied) - see http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=1051&query.id=148409#... 

The Backup Watchdog Timer in other V2 MCU parts (like Kirin3) is much improved. See http://www.utasker.com/forum/index.php?topic=505.0

Regards

Mark

www.uTasker.com
- OS, TCP/IP stack, USB, device drivers and simulator for M521X, M521XX, M5221X, M5222X, M5223X, M5225X. One package does them all - "Embedding it better..."

[MCF52233]

Thanks.
I also read given link by u n it is really very helpful.
Now i hv working watch dog time out reset.Only my mistake was i use ICR7 rather than ICR8.
When CWT = 0 i.e. for 2^9 bus cycles then how much actually time is mean for operating on 60Mhz???

Thanks once again for ur valuable time for the entire forum.