QSPI on MCF5329

[min]

Hi,

  I am having problems getting QSPI going on logicdp eval board here is my code

void SpiInit()
{ 

 MCF_QSPI_QMR = 0;
 MCF_QSPI_QMR |= MCF_QSPI_QMR_MSTR                      //Master mode; must be one
                               |MCF_QSPI_QMR_DOHIE                     //high-z b/w transfer          
                               |MCF_QSPI_QMR_BITS(0x08)            //8 bits transfter size
                                |MCF_QSPI_QMR_CPOL                  //CPOL: inactive spi clock state 
                                                                                            //is high
     |MCF_QSPI_QMR_BAUD(0x02);//baud rate
                                                                                           //CPHA not set (0)
                                                                                         //CPHA: data captured on leading
                                                                                          //edge.
           
 MCF_QSPI_QDLYR = 0;
                                                                                          //nothting to transfer SPE=0
                                                                                          //QCD=0 no clock delays
                                                                                         //DTL=0 no inter transfer delays
 MCF_QSPI_QIR = 0;
 MCF_QSPI_QIR |= MCF_QSPI_QIR_ABRTL
     |MCF_QSPI_QIR_WCEF                                           //write collision interrupt clear
     |MCF_QSPI_QIR_ABRT                                            //Abort interrupt clear
     |MCF_QSPI_QIR_SPIF;                                             //QSPI finished interrupt clear
                                                                                         //WCEFB: Write collision access
                                                                                         //err disabled=0
                                                                                        //ABRTB: Abort access err disabled
                                                                                          //=0
                                                                                       //Reserved=0;
                                                                                      //ABRTL: Abort lockout =1 =>QWR[SPE]
                                                                                         //=disabled.
                                                                                      //WCEFE: Write collision interrupt
                                                                                     //disabled=0
                                                                                      //ABRTE: Abort interrupt
                                                                                      //disabled=0
                                                                                    //Reserved=0
                                                                                      //SPIFE: finished interrupt
                                                                                   //disabled=0
                                                                                        //Reserved:XXXX
                                                                                        //WCEF: Write collision err flg=X
                                                                                           //1 to clr
                                                                                           //ABRT: Abort flg=X 1 to clr
                                                                                             //Reserved: X
                                                                                        //SPIF: SPI done:X 1 to clr.
 MCF_QSPI_QWR = 0;
 MCF_QSPI_QWR |= MCF_QSPI_QWR_CSIV;
                                                                                        //Halt=0
                                                                                    //WREN=0: Wrap around disabled;
                                                                                      //WRTO=X: Wrap around location
                                                                                     //CSIV=1: CS active state is low
                                                                                     //ENDQP=0=XXXX: endqueue point
                                                                                    //CPTQP==XXXX: Completed queue ptr=read
                                                                                          //only.
                                                                                       //NEWQP=XXXX: Startqueue ptr location

           
  
          
}

/**************************************************************************************************/

PutData(int sample)

{

 MCF_QSPI_QAR = 0x0020;
           //first cmd address
 MCF_QSPI_QDR = 0;
 MCF_QSPI_QDR |= MCF_QSPI_QDR_QSPI_CS0;
                                                                                         //CONT=0:CS inactive after word worth tx
                                                                                      //BITSE=0:8 bit tx can use one also as QMR[BITS]
                                                                                       //is defined appropriately
                                                                                       //DT=0:delay after tx set to default reset val.
                                                                                //DSCK=0:CS to clk delay set to 1/2 the clk period
                                                                                //QSPI_CS=E: CS number
                                                                                  //Reserved(0-7)=0
 
 MCF_QSPI_QAR = 0x0000;
                                                                                    //first tx RAM entry

 MCF_QSPI_QDR = cmd;
                                                                                          //sample data
 MCF_QSPI_QWR = 0x1F00;
                                                                                    //Halt=0
                                                                                  //WREN=0: Wrap around disabled;
                                                                                   //WRTO=X: Wrap around location
                                                                                   //CSIV=1: CS active state is low
                                                                                     //ENDQP=0=XXXX: endqueue point
                                                                                     //CPTQP==XXXX: Completed queue ptr=read
                                                                                   //only.
                                                                                     //NEWQP=XXXX: Startqueue ptr location
           
 MCF_QSPI_QDLYR |= MCF_QSPI_QDLYR_SPE;
                                                                                        //set data ready flag for tx to occur
}

What am i doing wrong....nothing happens when I put a logic analyzer on the pins.... i dont have any interrupt handler and I dont think I need any? 

Also is there a sample code for SSI driver?

Regards and thanx in advance

Message Edited by min on 2007-06-07 12:46 AM

[mjbcswitzerland]

Hi Min

Have you configured the ports to be QSPI?

Eg. (on the M5213)

    PQSPAR |= 0x0014;          // Set QSPI_CLK, QSPI_DIN on QS port

The above example doesn't use DOUT...

Here is some complete working code which simply conffigures and reads a number of bits from a shift register (including controlling latch via CS output). Perhaps you will see something else..(?)

Code:

// Read the Card ID via QSPI, which is also configured here//extern unsigned char fnGetCardID(void){    PQSPAR |= 0x0014;                                                    // Set QSPI_CLK, QSPI_DIN on QS port        PORTQS &= ~(QSPI_CS0_LINE);                                              DDRQS |= QSPI_CS0_LINE;                                              // Drive CS line low                   QMR = (QSPI_MSTR | QSPI_16BITS | QSPI_CPOL | QSPI_CPHA | QSPI_BAUD_RATE_FAST); // set master mode with 16 bit transfers at 10MHz clock    QAR = QSPI_COMMAND_RAM_0;                                            // Set address to first control location    QDR = (QSPI_QUEUE_8BIT | QSPI_CS_3 | QSPI_CS_2 | QSPI_CS_1 | QSPI_CS_0); // no chip select since we control it via port - 8 bit access    QAR = QSPI_TRANSMIT_RAM_0;                                           // Set address to first transmit location    QDR = 0xffff;    QWR = ((0<<QSPI_START_SHIFT) | (0<<QSPI_END_SHIFT));                 // Starting at queue 0 send/receive one entry    PORTQS |= (QSPI_CS0_LINE);                                           // drive CS high            QDLYR = QSPI_SPE;                                                    // Start transfer - dummy 0xffff will be sent and data bits read in    while (!(QIR & QSPI_SPIF)) {};                                       // wait for transfer to complete    QIR = QSPI_SPIF;                                                     // clear interrupt flag        QAR = QSPI_RECEIVE_RAM_0;                                            // Set address to first receive location    return (unsigned char)QDR;                                           // return the read value}

Best regards

Mark Butcher

www.uTasker.com
 

 

[min]

Mark,

   Thanks I was indeed not setting up the port, however even after configuring it i am not seeing any response.  No clock, no data!?  Did you spot a problem in my code?  I've not used your code yet, but I dont understand why mine is not working in the first place...I think there is someother problem...any other ideas?

Ok after I wrote the above, I started to look at the registers as the code executes.  I can see the QIR value turn to 0x0001 i.e. SPIF bit is set which should mean that the data has been sent out.  Still dont see anything on the pins???  QWR reads 0x0ff0 indicating that the current pointer is at the end pointer location F (I;ve modified the code in as much as what i send out)

Regards,
Minhaj

Message Edited by min on 2007-06-07 03:15 PM

[Kremer]

 Actually CSIV bit determines the CS state of all 4 pins when QSPI is not driving any signal. Try to let the device endpoint allways enabled to first try to interface to it alone in the bus, or try to set QWR to add short delays between CS driving and the clock and data signals.

 I think you are configuring the  QWR register to execute all 16 words of transfer ram, instead of try to execute only one command, wich is as you configured it, try to use it instead:

MCF_QSPI_QWR = 0x1000;

Also, after start a transfer setting SPE, it´s recommended to wait for the signal to be finished by waiting for the SPIF flag and then clearing it to finish correctly the transmit part.

 It works fine for my experience on 52235, maybe it can help.

Regards

[min]

Kremer,

  Thanx did not get a chance to check your post for sometime here.... I did get QSPI going  here is the code for anyone who may need it...I have not cleaned it up since I am trying SSi to work now but it works overall I am not able to send from the first entry of Queue last I tested it...so I am using queue entry 1 on.....does anyone know why writting to SSI registers (e.g. CR reg) not allowed even in supervisor mode??

Code:

 /***************************************************************************SpiInit: Sets up the SPI connection.** QMR must be set before the port is turned into QSPI port as that would* maintain the clk in a high state.***************************************************************************/void SpiInit(){  MCF_QSPI_QMR = 0;  MCF_QSPI_QMR |= MCF_QSPI_QMR_MSTR  //Master mode; must be one     |MCF_QSPI_QMR_DOHIE  //high-z b/w transfer               |MCF_QSPI_QMR_BITS(0) //16 bits transfter size     |MCF_QSPI_QMR_CPOL  //CPOL: inactive spi clock state            //is high     |MCF_QSPI_QMR_CPHA             //CPHA: data changed at leading           //edge.     |MCF_QSPI_QMR_BAUD(0x4b);           //     |MCF_QSPI_QMR_BAUD(0x0F);//baud rate           //CPHA not set (0)           //CPHA: data captured at leading           //edge./***********  DSCR_QSPI = 0x02;           //drive strength//; PPDSDR_QSPI = 0xC0F; PPDSDR_QSPI = 0xF0F;           //output pin direction.//; PODR_QSPI = 0xC0F; PODR_QSPI = 0xF0F;           //set all pins high PDDR_QSPI = 0xC0F;// PDDR_QSPI = 0xFCF;           //sets the direction (input=0) PAR_QSPI = 0xC3F0;            //sets the port to QSPI ************/                     // Set QSPI_CLK, QSPI_DIN on QS port            MCF_QSPI_QDLYR = 0;           //nothting to transfer SPE=0           //QCD=0 no clock delays           //DTL=0 no inter transfer delays MCF_QSPI_QIR = 0; MCF_QSPI_QIR |= MCF_QSPI_QIR_ABRTL     |MCF_QSPI_QIR_WCEF  //write collision interrupt clear     |MCF_QSPI_QIR_ABRT  //Abort interrupt clear     |MCF_QSPI_QIR_SPIF;  //QSPI finished interrupt clear           //WCEFB: Write collision access           //err disabled=0           //ABRTB: Abort access err disabled           //=0           //Reserved=0;           //ABRTL: Abort lockout =1 =>QWR[SPE]           //=disabled.           //WCEFE: Write collision interrupt           //disabled=0           //ABRTE: Abort interrupt           //disabled=0           //Reserved=0           //SPIFE: finished interrupt           //disabled=0           //Reserved:XXXX           //WCEF: Write collision err flg=X           //1 to clr           //ABRT: Abort flg=X 1 to clr           //Reserved: X           //SPIF: SPI done:X 1 to clr. MCF_QSPI_QWR = 0; MCF_QSPI_QWR |= MCF_QSPI_QWR_CSIV;//PPDSDR_QSPI = 0x38;//PODR_QSPI = 0x38;           //Halt=0           //WREN=0: Wrap around disabled;           //WRTO=X: Wrap around location           //CSIV=1: CS active state is low           //ENDQP=0=XXXX: endqueue point           //CPTQP==XXXX: Completed queue ptr=read           //only.           //NEWQP=XXXX: Startqueue ptr location/*            DSCR_QSPI = 0x02;           //drive strength PPDSDR_QSPI = 0x3F;           //output pin direction. PODR_QSPI = 0x3F;           //set all pins high PDDR_QSPI = 0x3B;           //sets the direction (input=0)*/            PAR_QSPI = 0xFFF0;           //sets the port to QSPI// MCF_QSPI_QDLYR = (0|MCF_QSPI_QDLYR_QCD(0x4b)|MCF_QSPI_QDLYR_DTL(9)); } /***************************************************************************SpiInit: Sets up the SPI connection.****************************************************************************/int PutBuf(unsigned char cmd, unsigned char num_bytes){ static unsigned int tx_in_proc=0;  int i; int cmd1;    cmd1 = 0x10aa; num_bytes = 10; //PPDSDR_QSPI = 0x38;//PODR_QSPI = 0x38;           //set all pins high// MCF_QSPI_QIR |= MCF_QSPI_QIR_SPIF;           //clear the SPIF bit            if (!(MCF_QSPI_QIR & MCF_QSPI_QIR_SPIF) && tx_in_proc) {  return (0);           //dont do anything if we are still in the process of           //sending data.   } tx_in_proc = 0;           //init the tx in process flag              if  ((MCF_QSPI_QIR & MCF_QSPI_QIR_SPIF))  printf("Alhamdulillah!!!!!!!!!!\r\n");  MCF_QSPI_QAR = MCF_QSPI_QAR_ADDR(0x20);           //first cmd address MCF_QSPI_QDR = MCF_QSPI_QDR_BITSE;           //BITSE=1:Tx QMR[BITS] count of data                 //CONT=0:CS inactive after word worth tx           //DT=0:delay after tx set to default reset val.           //DSCK=0:CS to clk delay set to 1/2 the clk period           //QSPI_CS1-3=0: all driver low           //Reserved(0-7)=0        for (i=0;i<num_bytes;i++) {  MCF_QSPI_QDR = /*MCF_QSPI_QDR_CONT        |*/MCF_QSPI_QDR_BITSE;           //BITSE=1:Tx QMR[BITS] count of data        /*|MCF_QSPI_QDR_QSPI_CS2);*/           //CONT=1:CS inactive after tx of queue entries           //DT=0:delay after tx set to default reset val.           //DSCK=0:CS to clk delay set to 1/2 the clk period           //QSPI_CS1-3=0: all driver low           //Reserved(0-7)=0          }                        MCF_QSPI_QAR = MCF_QSPI_QAR_ADDR(1);           //first tx RAM entry// MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0F00);           //reg addr F           //Rest the Codec// MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x8aaa);// MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x1E00);           //Reset MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0000); MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0200); MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x05F9); MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x07F9); MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x080A);//check!!!!! MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0A08);//check!!!!!  MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0C01); MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x0E42);           //Dig interface format           //Master=1           //left right swap disabled=0           //LRCIN high for right ch=0           //input len 16 bits=00           //I2S mode=10 MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x1018);           //Sampling rate ctrl           //for 32khz with 12Mhz MCLK MCF_QSPI_QDR = MCF_QSPI_QDR_DATA(0x1201);           //Dig interface activation MCF_QSPI_QWR = (0|MCF_QSPI_QWR_CSIV      |MCF_QSPI_QWR_ENDQP(num_bytes)      |MCF_QSPI_QWR_NEWQP(1));           //Halt=0           //WREN=0: Wrap around disabled;           //WRTO=X: Wrap around location           //CSIV=1: CS active state is low           //ENDQP=0=XXXX: endqueue point           //CPTQP==XXXX: Completed queue ptr=read           //only.           //NEWQP=XXXX: Startqueue ptr location            MCF_QSPI_QDLYR |= MCF_QSPI_QDLYR_SPE;           //set data ready flag for tx to occur  while  (MCF_QSPI_QIR & MCF_QSPI_QIR_SPIF != MCF_QSPI_QIR_SPIF); while  (!(MCF_QSPI_QIR & MCF_QSPI_QIR_SPIF));//  printf("Alhamdulillah\r\n");   tx_in_proc = 1;                      //set tx in process flag MCF_QSPI_QIR |= MCF_QSPI_QIR_SPIF;           //clear the SPIF bit MCF_QSPI_QAR = 0x0010;  tx_in_proc = MCF_QSPI_QDR;  /*******            MCF_QSPI_QDR = 0; MCF_QSPI_QIR |= MCF_QSPI_QDR_QSPI_CS0;           //CONT: CS inactive after a word           //=0           //BITSE: 8 bit tx QMR[BITS] ignored           //=0           //DT: delay after tx=0 =>default           //reset val           //DSCK: CS to clk default 1-1/2 clk           //=0           //Our codec chip =appropriate CS #           //Reserved=XXXXXXXX// MCF_QSPI_***********/ }

 

 

Regards,

--
Alban Edit: Code format.

Message Edited by Alban on 2007-06-14 11:40 AM