QSPI Interrupt service routine is not getting fired

[nilesh_khunte]

Hi,

I am using MCF5282 Evaluation board for development

I am writing a SPI interrupt based driver for MCF5282 controller

Functional QSPI Description:-

The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM,

and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI

interrupt register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.

Our Problem:-

It sets on the QSPI finish flag in QIR register once QSPI completes all the commands in the queue

but interrupt is not getting fired .I have enabled the SPIFE bit in QIR register ie 1-QSPI interrupt enabled.

I have done the following changes 

1)      Vectors5282.s File

vector52:   .long _QSPI_SPI_TransmitInterrupt /* QSPI Transmit*/

Interrupt Vector Determination

18    QSPI    Multiple QSPI interrupt    See QIR description

For INTC0, vector_number = 64 + interrupt source number

For QSPI= 64+18 =82 (decimal) 52H(Hex)

2)      QSPI module  .c  File

#pragma interrupt on

void QSPI_TransmitInterrupt(void)

{

}

#pragma interrupt off

3)      In initialization routine I am doing the below things

A) MCF5282_INTC0_ICR18 = MCF5282_INTC_ICR_IL(4) | MCF5282_INTC_ICR_IP(2 ); // Level and priority

B) MCF5282_INTC0_IMRL &= ~MCF5282_INTC_IMRL_INT18;  // Clear mask bit for this interrupt

Please let me know if i missed any step  

Regards

Nilesh

[TomE]

> Please let me know if i missed any step 

Nothing onbiously missed.

I'd check the values in all relevant registers with a debugger to make sure all the register definitions are correct. If you don't have a debugger, print the registers out (the relevane interrupt masks, status, ICR and so on).

Make sure all your ICR registers have UNIQUE IL and IP values. You can't have any ICRs with the same values.

Examine the interrupt table and make sure "vector52" is at the address you expect (0x52 * 4).

I'd suggest that, with the CPU IPL set to IPL7, do the following in the debugger or write code to do this:

1 - Print out IPRL0, IPRM0, QIR.

2 - Start the QSPI, and wait for QIR[SPIF] to set.

3 - Check to see if IPRL0[18] has now set.

4 - Check to see that IRLR0 is now showing IRQ4 active.

5 - Read the Global SWIACK and LnIACK registers. Check the vector.

6 - Drop the CPU IPL to zero (or less than 4), the interrupt should trigger.

You could also use INTFRCL0 to try and force the interrupt from within the controller.

Following the above should find where it isn't working.

Tom