Possible to atomically disable interrupts during initial ISR handling?

[DaveRahardja]

I've seen the following code at the entry point of several 52xx ISRs:

_isr:
    MOVE.W #0x2700,SR ; Disable interrupts
    ...

My question is: is it possible for another interrupt to "sneak in" right after the exception frame is pushed on the stack, but just before that first instruction is executed?

The V2 Core documentation says that exception handling terminates when the first instruction in the interrupt handler is FETCHED, so I'm assuming that the first instruction will ALWAYS be executed before another exception can be handled. I just want to make sure this is so.

Message Edited by Dave Rahardja on 2007-02-2410:22 PM

[cote]

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically intended for use as the first instruction of an interrupt service routine which services multiple interrupt requests with different interrupt levels. For more details see the ColdFire Family Programmer’s Reference Manual.

[DaveRahardja]

What settings must I make for CodeWarrior to accept the ISA A+ instructions?