Multiplexed FlexBus and non-shared SDRAM (MCF532x/7x)

[w_wegner]

Hi,

sorry if this is in fact obvious, but I would like to get this clarified before trying to test it myself in hardware...

When operating the devices (MCF532x/537x and probably most 52xx, too) in non-shared mode for (m)DDR, D15..D0 are mapped to D31..D16 internally. Is this a logical or a physical mapping, i.e. what happens to the multiplexed address bits? Is A31..A16 output in this mode, or A15..A0?

I see reasons for both possibilities, so maybe somebody who is using this configuration could comment on it.

Best regards,
Wolfgang

PS: Just in case someone wonders about the pros for both variants: outputting A15..A0 would give the possibility to completely omit routing the address bus to more sophisticated slave devices, while outputting A31..A16 would extend the usable address range over the line A23 that is present in hardware.

[w_wegner]

It´s always good to have nice FPGA colleagues... :smileyhappy:

So after my colleague implemented the DEMUX in the FPGA I can now confirm
that in fact for split bus mode the lower 16 address lines (A15..A0) are
multiplexed onto the FlexBus data lines.

I am not sure if this happens by coincidence or intention, but of course
it would be nice if it could be stated clearly in future reference manuals
what is the intended behaviour to be able to rely on such nice features.

Regards,
Wolfgang