I am using MCF548x (MCF5480) coldfire processor. I have few clarifications:
1)In the Reference manual(MCF5485RM), under Section 1.4.5 PLL and Chip Clocking Options, it is mentioned that MCF548x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz but the below table Table 1-2. references the frequencies from 25 Mhz to 50 Mhz. What does 30–66.66 MHz frequences for ClockIn implies?
2) Second there are options for Clock Ratio as 1:2 for different values of AD[12:8], whether it implies that for CLK frequency range 25.0 to 41.67 that AD[12:8] in the hardware has to be configured as 00101 and CLK frequency range 41.67-50.0 that AD[12:8] in the hardware has to be configured as 00011 to achieved the desired Core frequencies even though the Clock Ratio is1:2 ?
3. We are using 28.6363 Mhz which is above the specifications, as mentioned by NXP in one of the previous post of mine, but for clarification for other values of AD[12:8] whether this can be achieved. For other value of AD[12:8] apart from the ones listed in table whether there are any other frequency ranges.?
4. There is one more document in NXP search window for MCF548X(MCF5485PB) ,whether it is different from MCF548x (MCF5485RM) since the clockin tables are entirely different even though they are coldfire processors
> We are using 28.6363 Mhz which is above the specifications, as mentioned
> by NXP in one of the previous post of mine
Nothing from NXP there on you "overclocking" the CPU core, the buses and all of the peripherals. I said that (and I'm not from NXP).
There's a nice graph in the Reference Manual on Page 10-2 called "Figure 10-2. CLKIN, Internal Bus, and Core Clock Ratios".
If you're using 28MHz then you should be running the 1:2 ratio. If you're running 1:4 then the only valid, reliable and supportable clock frequency is 25MHz.
Your original question was that:
> After around three hours run, the SLT1 timer is unable to trigger the interrupt.
The obvious thing to test is to run the CPU at a LEGAL Frequency (either put a 25MHz clock on the board or reduce the divider to 1:2) and then see if it fails after a few hours (or days).
> Second there are options for Clock Ratio as 1:2 for different values of
> AD[12:8], whether it implies that
It doesn't "imply", it clearly states that you have to do that. I think you're asking "why?". The different settings (for the same divider) probably change the PLL filters so ir can lock properly to the different input frequency ranges.
1> Please refer MCF5485RM(Rev. 5 4/2009) page66 Table 2-4. MCF548x Divide Ratio Encodings about CLKIN clock frequency.
The PLL module has capability to provide high clock frequency (> 200MHz).
Based on MCF548x core clock frequency up to 200MHz, there with CLKIN input clock frequency Max. is 50MHz.
2> There with two AD[12:8] setting of same 1:2 clock ratio, the difference based on Max. core clock frequency range. For customer is using MCF5480 (Max. clock frequency is 166MHz), customer need to refer and use AD[12:8] setting with 00101.
3> Please refer second answer to select suitable AD[12:8] setting.
4> MCF5485PB (Product Brief) Rev. 1.3, 09/2004, which info is not updated. Please refer MCF5485RM(Rev. 5 4/2009) for the latest CLKIN input clock requency requirement. Thanks.
Sorry for the documents issue brings those confusion and inconvenience.