I am experiencing a problem with longer transfers with the DSPI.
when I transfer 64 bits or less, everything works OK.
More than that, the operation is unreliable.
I interpret the databook as 16 longwords meaning 16 writes to the DTFR, each containing 16 bits of data + the chipselect etc., so I should be able to transfer 256 bits with no problem.
Can someone offer some suggestions where to look?
I tries to track what is happening using the DSPI Tx FIFO Debug registers DTFDRn, but got completely lost trying to track what is happening.
This is the part of the manual I am referring to:
27.7.2.4 Tx FIFO Buffering Mechanism
The Tx FIFO functions as a buffer of SPI data and SPI commands for transmission. The Tx FIFO holds
from 1 to 16 longwords, each consisting of a command field and a data field. SPI commands and data are added to the Tx FIFO by writing to the DTFR. Tx FIFO entries can only be removed from the Tx FIFO by being shifted out or by flushing the Tx FIFO.
