So far I've learnt that there is an error in the manual regarding the internal SRAM but I have not found out what the solution is.
I believe it is only possible to have either code or data in the SRAM but not both when connected directly to the core.
It's about time a new manual was released for this processor since there are so many errors in the existing one (Rev 2) or at the very least an updated list of errata.