MCF5441x FB_CLK Spec clarification

[ewanwordsworth]

Hello.  

I'm wondering if anyone can confirm or clarify the FlexBus Clock (FB_CLK) specification on

the MCF5441x series of parts please?

In the datasheet the FB_CLK is defined as SYSCLK / 2, Sysclk being the core frequency

which is specified at min 120Mhz, Max 250Mhz. From that, I would assume that the FlexBus Clock

(being sys/2) would be min 60Mhz, Max 125Mhz, however, the spec in the data sheet states

that min = 60Mhz (as expected) but the max is [only] 100Mhz.

This leads me to wonder :

a).. Is the 100Mhz max supposed to be 125Mhz? or,

b).. Is the 100Mhz max because of a pin driver limitation (slew rate / loading etc?)

c).. if the max is actually 100Mhz, and FB_CLK is always Sys/2, then perhaps the core clock

      must be limited to 200Mhz while the Flexbus is enabled?

d).. perhaps the statement that FB_CLK = SYS/2 is misleading and they are separately derived 

      clocks from the VCO frequency and FB_CLK must be half or less than half of the SYS clock?

I'm suspecting that the answer is 'd' but the diagrams and text are confusing, always talking about FB_CLK

being SYS/2 - for example the MCF5441x Reference Manual (Rev 4) in Table 8-4 ( PLL_DR Field Descriptions),

for OUTDIV2, and Figure 8.1 (Device Clock Connections).

Thanks in advance for any help / comments.

[TomE · Accepted solution]

> In the datasheet the FB_CLK is defined as SYSCLK / 2,

You're looking at "Table 14. PLL electrical characteristics". That's the PLL specification and not the FB_CLK spec.

If you're using the Flexbus ("FB_CLK" is "FlexBus Clock"), then it's frequency is given in "Table 16. FlexBus timing specifications", and there it is a maximum of 62.5MHz.

In the Reference Manual in "Figure 8-1. Device Clock Connections", FB_CLK is "fsys/2 or fsys/4 depending on MISCCR2[FBHALF]". THAT'S how you drop FB_CLK to meet its or the FlexBus timing requirements.

I think you're right in that if you're using the FlexBus, then EITHER the CPU Clock has to be dropped to 125MHz if FB_CLK is that divided by 2, or to use a higher CPU clock speed then you need to use the divide-by-4 option.

If you're not using FlexBus, then you have to limit the CPU Clock to 200MHz to get FB_CLK to 100MHz on divide-by-2, or, then again, to get the CPU faster than that you have to use the divide-by-4 option.

There's a lot of flexibility, but coupled with a lot of restrictions. If your design is power limited but doesn't need the full 250MHz CPU speed then it might make sense to run it slower.

If you're using USB, then it has to have a completely separate 60MHz clock, which is very hard to generate, or you must run the CPU at 240MHz and FB_CLK at 60MHz. "Figure 8-1. Device Clock Connections" shows where the USB Clock comes from and its restrictions.

Ethernet needs 25MHz or 50MHz, and with a tight frequency requirement. This is usually met with an external crystal.

Tom

[ewanwordsworth]

Hi Tom.

Thanks for your quick response and detailed reply.

I've been evaluating MCF5445x vs MCF5441x for a design which has an FPGA attached via the FlexBus

and wanted to maximize the data rate. When I saw that the 5441x looked to have a max FB_CLK of 100Mhz,

it looked more attractive.  I'm glad that I had this clarified.

Best regards,

Ewan.

[TomE]

> FPGA attached via the FlexBus

The minimum number of clocks for a Flexbus read or write cycle is 4. It can "burst", but that only means that the "bursting" cycles can have less wait states than the first one.

There is also an unexpected latency from the CPU to the Flexbus. If the CPU is reading or writing "back to back" Flexbus accesses, then they might not be as fast as you'd expect on the external bus. The latencies and delays aren't documented anywhere, so you'll have to measure them yourself to see if the hardware can match your design requirements.

Tom