MCF5235 - Occasional startup failure

[nxf51434]

Hi guys, my customer met the low probability issue of startup failure with the BPKT level is pulled down during the rising process. That's the confusion that BKPT (BDM mode) is input and pulled up to vdd with a 4.7k resistor. Who controls the BKPT pin?

Additionally, I checked the customer schematic and found that the XTAL was floating, against to the description on the 782 page of the manual says that XTAL must be tied low in extern clock mode when reset is asserted, or clocks 'may be suspended indefinitely'. I'm not sure if this is the root cause.

[TomE]

We have multiple devices using the MCF5235. They're all the same basic design. They all have XTAL floating and are using an external oscillator, and we've never had any problems. Everything says BKPT is an input, so I don't know why it is going low like that. Are you sure there are no shorts to other signals on the board?

You have a 3ms rise time on VDD there. What's the timing of the RESET pin relative to those signals? Our design uses a separate POR chip that holds RESET low for a while after VDD has come up (and the oscillator has stabilised). Is your one doing that, or is it relying on the internal POR circuitry? What's the assertion of RSTOUT relative to those signals you're looking at. Both when it works and when it doesn't?

What's JTAGEN connected to? We have a 2k2 Pullup on that. If that is floating then the chip might get confused between JTAG and Debug modes.

Tom

[nxf51434]

Your information is helpful, appreciated!

[_angelo_]

hi nxf51434

from your diagram, it is not visible what's connected to BKPT. It is an input, active low, so i would eventually put a 4,7K pull up there, for testing.

Is it possible in your custom board some dirty or short brings the signal down ? 

Cheers 

[nxf51434]

I suggested customer pulled up JTAG_EN to reduce the risk of BKPT triggered by dirty signals. TKS!

[Hui_Ma]

Hi,

I checked customer board schematics with CLKMOD[1:0] equals 10 setting is used (normal PLL mode with external clock reference), which was mentioned at MCF5235 chip errata file with below description:

Please try with this workaround and check if it could fix the issue.

Wish it helps.

Mike

[nxf51434]

Hi Hui, I checked errata SECF131 and SECF163 before, customer design has already connected CLKMOD1 to RSTI, and the chip date date is xxxx1748, newer than the xxxx1031. 

[Hui_Ma]

Hi Stevens,

The BKPT pin is the input pin, which used to puts the core into a halted state after the current instruction completes.

I did a search with internal support records and could not find any info about this phenomenon. 

When customer connect the XTAL pin to GND, if that could reduce the failure happen frequence?

During the POR phase, if customer assert the MCF5235 reset button, if that could help to reduce the failure happen frequence? I want to check if external clock source could provide stable reference clock during PLL initialization phase.

If that issue is a single board issue? 

best regards,

Mike

[nxf51434]

The issue is not single board case and difficult to reproduce. XTAL pin was't drawn out due to BGA packaging. I'd advised customer to layout new board to reduce the risk. TKS!