Hi,
There is a PLL errata [SECF033: PLL Loss of Lock and Clock Jitter] at MCF5227x errata document.
This errata only affect the chip Rev. 1.1.
Please refer below picture about chip mask set realted chip version:
Hui_Ma_0-1658537197045.png
When the PLL lost of lock and chip does not run out of reset phase, the RSTOUT is low means the chip still run in reset phase, which should be reasonable.
Please check the different behavior of external crystal of working board vs. issue board.
If possible, could you change the issue board with a new crystal and check if that could fix the issue board.
Wish it helps.
Mike