MCF52236 and PLL

[Opalek]

Hello,

I have a problem with PLL:

uC works with Crystal 25MHz and PLL multiply by two (devide 8 [predivider] and then multiply by 16[MRD]) , so should be 50MHz.

Sometimes The uC wakes up in correct  frequency(50MHz) but sometimes runs faster...

Does anybody have that problem with this uC?

The same program on MCF52234 works perfect - always wakes up with 50MHz

Crystal works properly - 25MHz on EXTAL, PCB is correct, all peripheral capacitors are correct...

I think it must be problem of uC...

Best Regards

Pawel

[TomE]

What frequency is the CPU running at? Measure the CLKOUT pin. If you can't get to that, start a timer running and have it toggle a pin at a known rate, then measure that on different boards.

Are you reprogramming the PLL while running of the bypass clock?

Table 7-4. SYNCR Field Descriptions (continued)

Clock Source. Determines whether the PLL output clock or the PLL reference clock is to drive the system
clock. This bit is ignored when the PLL is disabled, in which case the PLL reference clock drives the system
clock. Having this separate bit allows the PLL to first be enabled, and then the system clock can be switched
to the PLL output clock only after the PLL has locked. When disabling the PLL, the clock can be switched
before disabling the PLL so that a smooth transfer is ensured.

Tom

[Opalek]

When I switched a signal to the pin (rectangle, 50% duty, period 1second) - if the PLL works properly (50MHz)

If PLL works faster the period is circa 600ms....

I tried SYNCR in each mode.... I set this register by Processor Initialization in Code Warrior, so I think, that the CLKSRC bit is set in properly moment...

Thank you for reply

Regards

Pawel