MCF51JM undocumented PTIMER bits of FTSR for security clear procedure

[JoziasdelRios]

On MCF51JM128 Reference Manual rev.2 page 89 there's a figure 4-15 which tells

the procedure for Clearing Security on a MCF51JM128 via the BDM port.

I've built my self an USB programmer, but a bug on it made my MCF51JM32VLD device secured, because

XCSR is reading as 0x87 and not 0x85 just after a POR with BKGD held low. So I know the device is secured.

I want to unsecure this device, doing a mass erase, but the procedure in the figure 4-15 is cryptic, as it tells

to write PTIMER bits to CSR3, and then PTIMER info would be transfered to FTSR.

But nowhere in the manuals FTSR and PTIMER names are defined. I figured out by MCF51EM256 Reference Manual that FTSR means "Flash Controller", but PTIMER is still foggy.

Can someone tell me what byte value should I write to CSR3 prior to write 0x97 to XCSR?

My MCF51JM32VLD device is halted after POR, so it's clock is FEI@10MHz. The flash divider value is 0x19 (25 decimal) as usual for this setup.

Thanks in advance.

Del Rios

[kef]

I think that 1) two pages figure 4-15 is broken. 2) page 89 should be removed, since mass erase is finished (and security is removed) on page 88. All you need to lauch mass erase procedure and let controller complete it.

You may take a look at MCF51QE manual. JM and QE have similar if not identical flash memories. Figure 4-15 in QE RM is similar to 1st page of figure 4-15 in JM RM.

(I'm not familiar with CFV1 BDM and am not sure about default FEI clock. I would double check if it's oscilator clock or maybe bus clock and how far it deviated while untrimmed. The best would be to determine bus clock frequency timing SYNC response.)

[JoziasdelRios]

Just as a side note, I've succeeded clear the security with "PTIMER bits" = 0xFF, but I've no idea what I'm really doing.