M5223X Edge Port interrupt priorities

[mjbcswitzerland]

Hi All

I am trying to clear up an issue with Edge Ports on M5223X.

The user manual states that the edge port consists of IRQ line 1..7, but there are 2 edge port control registers and all together IRQ1..15. I am assuming that there are this really 15 edge ports as defined.

It is stated that the edge port have a fixed mid point priority (0x8) for IRQ1..7, where the user can still define an interrupt level (1..7). No two interrupt sources should have the same level/prioity.
This means that if IRQ1..IRQ7 are used, each must have a differnet priority level from 1..7 and the one with level 7 will in effect become a NMI (can not be masked).

Has this been understood correctly?

The thing which is giving a bit of confusion is to do with the IRQ8..15 interrupts.
Are these also assigned a fixed mid pint priority or can the user define any mix of level and priority?
It does in fact seem logical that they are free since the IRQ1..7 would have already used up all the mid-level priority/level combinations.

But can any one give a definite answer??

Regards

Mark Butcher

[SimonMarsden_de]

Hi Mark

This is definitely NOT a definitive answer, but my reading is the same as yours. IRQ1-7 have fixed priorities, but IRQ8-15 are free and can be configured through Interrupt Controller 1 to have any levels / priorities.

As supporting evidence, I notice that there are 8 IRQs for the second EdgePort, and only 7 for the first. Since there is no level 8, I think they must be configurable.


Hope this helps


Simon

[mjbcswitzerland]

Hi Simon

Thanks for your input.

I am tending to believe the same (and am preparing to modify some code to suit).
So if no one can convince of the opposite - or of couse an expert can confirm (which would be the best case) - it looks as though this will become the definitive answer....

Regards

Mark

[Oriol_CiTCEA]

Hi Mark, Simon,

For IRQ1-7, you can't change priorities, neither levels, as long as Interrupt Control Registers (ICRn) 1 to 7 are Read Only registers (Reference Manual, 15.3.6), and Edge Port interrupts 1 to 7 are located at ICR0.1 to ICR0.7 (RM, 15.3.6.1).
By default, they are allocated at corresponding levels: IRQ1»level1; IRQ2»level2; ... (RM 15.1.1)
It's the same for ICR1.1-7, though those register have not any interrupt source associated.
On the other hand, Edge Port Interrupts 8 to 15 are related with ICR1.32 to ICR1.39 (RM, Table15-14), and thus, you can change levels and priorities for IRQ8 to 15.

There are not NMI in this Coldfire. All interrupts are source-maskable (IMRHn and IMRLn, at RM15.3.2), where the interrupt source is maked, regardless of levels and priorities.
Anyway, all interrupts at defined at level 7 have more priority than any program or interrupt routine (RM15.31), thus their code will be executed always the interrupt is not masked at IMRH/Ln register.

As far as I know
don't loose your head,

Oriol