How to connect slow peripheral to AD-Bus in mixed-voltage-designs?

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How to connect slow peripheral to AD-Bus in mixed-voltage-designs?

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opi
Contributor I

I´ve got the netburner module with Coldfire 54415 and i have to connect the TNT4882 Controller from NI.

 

This results in a mixed voltage design - Processor 3,3V, Peripherie 5 V.

 

I will use this one in a mode with 8-bit non-multiplexed AD- bus, /IRQ, /Reset, /CS, /RD and /WR signals.

 

My problems are:

a) What is a smart solution for generating /RD and /WR signal? My actual idea is, to generate these signals with NAND

74LVC132: /RD = !(!RD/WR & /CS), /WR = !(RD/WR & /CS)

b) I need a mixed-voltage driver for databus. An idea is 74LVC245A, but I cannot find a fitting signal for G (Enable).

c) Regarding contol-signals: I cannot interpret the timing of /BE[0..3]. Is it similar to /CS? Perhaps this one could fit.

 

Do You have a reference-design for connecting such a device in mixed-voltage-environments?

 

Thank You very much in advice,

Stefan

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miduo
NXP Employee
NXP Employee
a)  What is a smart solution for generating /RD and /WR signal? My actual idea is, to generate these signals with NAND 74LVC132: /RD = !(!RD/WR & /CS), /WR = !(RD/WR & /CS)

>> There are multiple ways that you could solve this problem. The best approach would depend on the exact timing that you need. Have you considered using the /FB_OE signal as the read pulse? You might be able to use that directly and do away with some external logic. For a write enable you might consider using a byte enable. I’m assuming you’re using the BLS=0 option for the FlexBus. If that is the case then /FB_BWE0 would assert for any write accesses to your 8-bit port. Just make sure to clear the CSCR[BEM] bit for any of the chip selects where you need to use it so that it will only assert for writes.

b)  I need a mixed-voltage driver for databus. An idea is 74LVC245A, but I cannot find a fitting signal for G (Enable).

>> I would think that you could use the chip select signal as the enable. If you have multiple devices that will be past the buffer, then you’d want to AND all of the chip selects for the buffered devices to create the enable.

c) Regarding contol-signals: I cannot interpret the timing of /BE[0..3]. Is it similar to /CS? Perhaps this one could fit.

>> Yes, if it is asserting /FB_BE would have the same basic timing as the /CS signal. Whether a given /BE signal asserts on a bus cycle will depend on the BLS configuration, CSCR[BEM], size of the access, and direction of the access. As I mentioned before, I think you’ll want to clear the CSCRn[BEM] bit so that the byte enable signal is used as /FB_BWE and asserts on writes only. This way you can use the signal as an active-low write pulse.

Do You have a reference-design for connecting such a device in mixed-voltage environments?

>> You might want to refer to the schematics for the M5275EVB (posted on our website). It’s a different processor, but that part uses a FlexBus module. On the EVB we use some dual-voltage buffers to translate signals from 2.5V to 3.3V and back.

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miduo
NXP Employee
NXP Employee
a)  What is a smart solution for generating /RD and /WR signal? My actual idea is, to generate these signals with NAND 74LVC132: /RD = !(!RD/WR & /CS), /WR = !(RD/WR & /CS)

>> There are multiple ways that you could solve this problem. The best approach would depend on the exact timing that you need. Have you considered using the /FB_OE signal as the read pulse? You might be able to use that directly and do away with some external logic. For a write enable you might consider using a byte enable. I’m assuming you’re using the BLS=0 option for the FlexBus. If that is the case then /FB_BWE0 would assert for any write accesses to your 8-bit port. Just make sure to clear the CSCR[BEM] bit for any of the chip selects where you need to use it so that it will only assert for writes.

b)  I need a mixed-voltage driver for databus. An idea is 74LVC245A, but I cannot find a fitting signal for G (Enable).

>> I would think that you could use the chip select signal as the enable. If you have multiple devices that will be past the buffer, then you’d want to AND all of the chip selects for the buffered devices to create the enable.

c) Regarding contol-signals: I cannot interpret the timing of /BE[0..3]. Is it similar to /CS? Perhaps this one could fit.

>> Yes, if it is asserting /FB_BE would have the same basic timing as the /CS signal. Whether a given /BE signal asserts on a bus cycle will depend on the BLS configuration, CSCR[BEM], size of the access, and direction of the access. As I mentioned before, I think you’ll want to clear the CSCRn[BEM] bit so that the byte enable signal is used as /FB_BWE and asserts on writes only. This way you can use the signal as an active-low write pulse.

Do You have a reference-design for connecting such a device in mixed-voltage environments?

>> You might want to refer to the schematics for the M5275EVB (posted on our website). It’s a different processor, but that part uses a FlexBus module. On the EVB we use some dual-voltage buffers to translate signals from 2.5V to 3.3V and back.

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