Help with MSCAN config

[Bloodhound]

Hi There,

I am trying to configure the MSCAN module in a MCF51JM32 to run at 500kbits from an 8MHz XTAL.

I don't think I have it right (well, it never see's any CAN messages).

Here's what I have: (referring to page 268 of MCF51JM128RM Rev2)

The MSCAN is configured to get it's clock source from the external crystal (CANCTL1, CLKsrc=0)

SYNC_SEG = 1

Time Segment 1 = 12

Time Segment 2 = 3

For a total of 16 Time Quanta

The formula in the Ref Manual is:

Bit Rate = fTq / (number ⋅ of ⋅ Time ⋅ Quanta)

I have no prescaler so the maths should be:

8,000,000 / 16 = 500,000.

Does that seem correct?

Thanks

[kef · Accepted solution]

Yes, bitrate is fTq/(1+ Timesegment1 + Timesegment2). But did you notice that TSEG1 bits are Timesegment1-1 and TSEG2 bits - Timesegment2-1?

Did you follow Table 11-35 recommendations? With timesegment2=3, recommended timesegment1 setting tops at 11. Try timesegment2=4(TSEG2=3) and timesegment1=11(TSEG1=10).

You can have problems receiving messages if message filters are not set up properly. It may be easier to verify baudrate sending any message to empty bus and measuring least pulse width. 1/Tleast will give you current bitrate setting.

To accept all messages just set all CANIDMR registers to 0xFF. '1' bit in mask register means that corresponding ID bit can have any value.

[Bloodhound]

Thanks for the reply Kef.

I had loaded the message CAN Acceptance Registers & CAN Mask Registers with $FF's figuring everything should get through.

I guess I was more after the clarification that the formula for working out the bit rate was correct for the Coldfire devices. Because on the HC08 devices the CAN module has it's XTAL derrived clock feed divided by 2, that doesn't appear to be the case for the Coldfire (from what I can make out in the ref manual).

What I can say it that when I have a 500kb CAN signal feeding in to the MCF the CSCIF (CAN Status Change Interrupt Flag) changes to '1' but the RXF(Receive Buffer Full Flag) never changes. So I am assuming that means it's seeing 'something' but nothing it considers as a valid Rx message.

Cheers,

Ross

[kef]

I don't know which HC08 derives CAN clock from XTAL/2, but S08D derives CAN clock either from XTAL/1 or from bus clock/1. And bus clock, when clocked from XTAL (no PLL or FLL engaged), is XTAL/2. It is the same on S12(X) and I think it is the same on MCF51.

[Bloodhound]

In the MC68HC908GZ8 manual it clearly shows in the clock routing diagram the MSCAN08 is getting a divide by 2 clock (prior to any prescaling).

MC68HC908GZ8

CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven from (see 16.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 16-7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 16-7).

[Bloodhound]

It was the TSEG1 & TSEG2 that needed fixing.

I ended up with 1(Sync) + 10(TSEG1) + 5(TSEG2) for a total of 16 Time Quanta.

Which calculates out to 500kbits at 8MHZ clk.