GPIO Pin during reset

[beckm1]

Hi all

On the project I am working at the moment I am using a MCF5373L processor.

At the beginning the processor stays in reset until a switch desactivate the reset. The switch is connected to the processor (pin FB_CS5, functions of the the switch are used when processor is running) and a CPLD (function of the switch is desactivating of the reset).

Found in a thread and also in the Reference Manual, the GPIO are digitial inputs. In the thread is written that a weak pull up is enabled during the reset.

(Link: https://community.freescale.com/message/69585#69585)

When I press now the button (connected over a PU to 3.3V to GND --> Low active), the signal which is connected to the CF and the CPLD only sinks from 3.3V to arround 3.1V.

I tried the same without CPLD (when the button is only connected to the CF) and the result is the same.

As it looks like, the GPIO are driven activly high during the reset. But I could not find a proper answer on that neither in the Reference Manual, nor in the Datasheet nor in the forum.

Is it like that and are there any possibilitys to change that? As I saw in the posted thread, there is no configuration register for that.

Thank you for helping!

[TomE · Accepted solution]

> On the project I am working at the moment I am using a MCF5373L processor.

> At the beginning the processor stays in reset until a switch desactivate the reset.

> The switch is connected to the processor (pin FB_CS5,

>

> Found in a thread and also in the Reference Manual, the GPIO are digitial inputs.

> In the thread is written that a weak pull up is enabled during the reset.

 >

> (Link: CFV2 gpio input pull-up on reset question?)

That thread documents the CFV2 chips. You're using a CFV3. There are a lot of differences.

Table 2.1 in the manual documents FB_CS5 as having a PRIMARY function of being a Chip Select and being an Output.

The reset function of this chip is controlled by:

13.3.5.3 Chip Select Pin Assignment Register (PAR_CS)

The Reset state of the PAR_CS5 bit (all chip selects, in fact) is for them to be configured as active chip selects.

Your hardware designer has connected the switch to a pin that is driven actively high during reset.

It won't act like a GPIO until the software has written to PAR_CS to change it.

You have to change the hardware to use a different pin (and check all the other pins you're using while you're at it), OR you could add a high value resistor between the pin and the switch so the reset level doesn't interfere with the switch's function during reset. Either way you have to change the hardware.

Tom

[beckm1]

> The reset function of this chip is controlled by:

>  

> 13.3.5.3 Chip Select Pin Assignment Register (PAR_CS)

>

> The Reset state of the PAR_CS5 bit (all chip selects, in fact) is for them to be configured as active chip > selects.

> Your hardware designer has connected the switch to a pin that is driven actively high during reset.

>  

> It won't act like a GPIO until the software has written to PAR_CS to change it.

Hello Tom

thank you for your answer.

I saw that the primary function of FB_CS5 (and all other chip selects) is being a chip select and that it acts as a output. But I could not see a 100% clearly if it is active driven or high Z.

But it actually makes sense this way. I will chose another pin, which acts as GPIO during reset.

beckm1