EPHYCTL0 initialization

[vale]

Hallo,

I've a question about EPHYCTL0 initialization:

in the Codewarrior sample code for M52235EVB mcf5223_sysinit.c, specifically in the routine mcf52235_gpio_init, I find the following lines:

//Enable EPHY module with PHY clocks disabled
 //Do not turn on PHY clocks until both FEC and EPHY are completely setup (see Below)
 MCF_PHY_EPHYCTL0 = (uint8)(MCF_PHY_EPHYCTL0_DIS100 | MCF_PHY_EPHYCTL0_DIS10);
 
 //Enable auto_neg at start-up
 MCF_PHY_EPHYCTL0 = (uint8)(MCF_PHY_EPHYCTL0 & (MCF_PHY_EPHYCTL0_ANDIS));

 //Enable EPHY module
 MCF_PHY_EPHYCTL0 = (uint8)(MCF_PHY_EPHYCTL0_EPHYEN | MCF_PHY_EPHYCTL0);
 //Let PHY PLLs be determined by PHY
 MCF_PHY_EPHYCTL0 = (uint8)(MCF_PHY_EPHYCTL0  & ~(MCF_PHY_EPHYCTL0_DIS100 | MCF_PHY_EPHYCTL0_DIS10));

In the Freescale MCF52235RM manual, it is recommended to "clear" DIS100 and DIS10 bits before setting EPHYEN to 1.

1) What is intended by saying "clear": shall I set those bit to 0 (making EPHY determine PLL states)?

 Why then the sample code puts those bit to 1 disabling PLLs?

2) Is the state of DIS10 and DIS100 latched when EPHYEN is set to 1? If it is, why in the sample code EPHYCTL0 is changed AFTER EPHYEN has already been set?

Thank you for any clarification.

Valentina 

[mjbcswitzerland]

Hi Valentina

The PHY clocks are disabled when set to '1' so I think that you can interpret this as 'disabled'.

The PHYADD[4:0] and ANDIS are latched to the MII register when the EPHYEN is set, but this has nothing to do with the PHY clocks.

Note also a 360us delay after setting EPHYEN before the MII registers can be configured via MDIO.

Regards