I've not used this part but it looks like the part is able to do this (from the ref man):
18.4.3.3 BDM in Run and VLPR Mode
If the MCU is unsecure and BDM mode is enabled, then the MCU can be fully debugged using the BDM in RUN and VLPR modes. If XCSR[ENBDM] = 0, before entering active BDM mode, the host must write XCSR[ENBDM] = 1 before sending a BACKGROUND command.
Have you checked which clock you are using for the BDM clock:
21.4.6 MCG Background Debug Controller Clock
The MCG Background Debug Controller Clock (MCGBDCCLK) provides a clock source to the Background Debug Controller (BDC). This clock is driven by either the SYSCLK or the 4 MHz internal reference clock (IRC), as selected by the XCSR[CLKSW] bit in the V1 ColdFire debug module.
Shaun