DSPI as GPIO register/pin relationship in MCF5445x

[w_wegner]

Hi all,

I am trying to debug some things by bit-banging the DSPI pins on my board.

While doing so, I think I found a problem in the documentation of the DSPI Pin Assignment Register PAR_DSPI (page 16-28/PDF 368) of MCF54455RM Rev. 5.

The documentation reads:

Bit 0: PAR_SCK

Bit 1: PAR_SOUT

Bit 2: PAR_SIN

But I think it should be

Bit 0: PAR_SOUT

Bit 1: PAR_SIN

Bit 2: PAR_SCK

Can anybody confirm this, or do I have to debug further?
(I also have a simple serial flash connected to DSPI and can access it using the DSPI peripheral, so the pinout in our layout should be correct.)

Best regards,

Wolfgang

[w_wegner]

Hi again,

now I found where this confusion originates from:

The pin/GPIO index is correct in the  external signal description (pp. 2-2ff, 16-4ff), but the mapping in the corresponding PAR_xxx register is different for some units (namely, SSI and DSPI, pp. 16-28f, 16-34).

It would be nice if freescale could comment on this (and leave a comment in the datasheet) if this different mapping is really intentional or to correct the PAR_xxx bit definitions to clarify this part of documentation.

Regards,

Wolfgang