Core watchdog timer on CF5235 and CF5313

[oloft]

I am trying to verify code that enables the core watchdog timer on the M5235EVB. The code is later supposed to run on a CF5213. Development environment is CodeWarrior for Coldfire ver. 6.2. Target project is based on the M5235EVB stationary.

This is a central part of the (non functional) code:

Code:

#include "m523xevb.h"..MCF_SCM_CWCR = MCF_SCM_CWCR_CWE |    // Enable WDT       MCF_SCM_CWCR_CWT(1) | // 2^19 bus cycles.        MCF_SCM_CWCR_CWTA |    // Enable Transfer Ack.       MCF_SCM_CWCR_CWTAVAL |       MCF_SCM_CWCR_CWTIC;

 

The code above should set up the WDT make a vector call on time out to wdtISR.

Code:

__declspec(interrupt) void wdtISR( void ){ MCF_RCM_RCR |= MCF_RCM_RCR_SOFTRST; // Set software reset request bit.}

I have modified the vector table to contain ther address to wdtISR and all stray interrupts are catched by the default ISR implementations from the stationary. The vector table in RAM is verified to be correct.

What happens is that the processor locks on time out, no call to the wdtISR or any other ISR ever happens and trying to break the execution with the PE-USB debugger results in error messages. If MCF_SCM_CWCR_CWTA is not set the processor does not lock but nor does the watch dog timer time out.

Does any one know how the core watch dog timer and other moudles should be configured for a proper operation?

Regards

Olof

[oloft]

Issue solved.

    MCF_INTC0_IMRL  &= ~( MCF_INTC0_IPRL_INT8 | 1 ); // Enable Irq 8 (bit 0 should allways be 0)

was omitted from the initiation of the interrupt controller. This was the setting that worked for me:

    MCF_INTC0_ICR8 = MCF_INTC0_IACKLPR_PRI(7) |    MCF_INTC0_IACKLPR_LEVEL(7);
    MCF_INTC0_IMRL  &= ~( MCF_INTC0_IPRL_INT8 | 1 ); // Enable Irq 8 (bit 0 should allways be 0)

Hope this helps someone.