This message contains an entire topic ported from the WildRice - Coldfire forum. Freescale has received the approval from the WildRice administrator on seeding the Freescale forum with messages. The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value as you search for answers to your questions. Freescale assumes no responsibility whatsoever with respect to Posted Material. For additional information, please see the Terms of Use - Message Boards and Community Forums. Thank You and Enjoy the Forum!
Nov 3, 2005, 8:46 AMPost #1 of 2 (19 views)
Copy Shortcut
[ColdFire] Coldfire interrupt priorities in uClinux Can't Post
--------------------------------------------------------------------------------
I'm building a counter driver utilizing the GPT ports of the mcf5282.
As part of the driver, I'm assigning an interrupt for every IC, so the user
has the option of doing a slow, soft counter on all 4 channels.
It works fine, unless I get 2 of these interrupts simultaneously.
When this happens the processor starts generating an interrupt 127, which is
actually listed as "unused" in the manual, which is never cleared, so just
constantly loops the default interrupt handler routine.
The manual goes on to say that I should not be assigning the same interrupt
level,priority combo to more than one vector (which I am).
Is there any type of organization in the current tree that is supposed to
protect this from happening with drivers? Or are we just playing the odds
that in most cases 2 interrupts won't happen at exactly the same time?
Interestingly enough IRQMRH = 0xff7f0ff0, so vector 127 should be masked, yet
it is still fireing.
I suspect the processor really doesn't like 2 interrupts with the
samelevel,priority happening simultaneously.
thx,
NZG.
--------------------------------------------------------------------
Nov 3, 2005, 9:03 AM
Post #2 of 2 (19 views)
Copy Shortcut
Re: [ColdFire] Coldfire interrupt priorities in uClinux [In reply to] Can't Post
--------------------------------------------------------------------------------
Hi NZG. You are right, don't do that! It is your responsability to make
sure no two interrupt sources have the same IL/IP.
Marc
NZG wrote:
>I suspect the processor really doesn't like 2 interrupts with the
>samelevel,priority happening simultaneously.
Message Edited by Dietrich on 04-03-2006 11:02 AM
Message Edited by Dietrich on 04-04-2006 09:15 PM
