ColdFire 5484 R/W line will not return high

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ColdFire 5484 R/W line will not return high

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mr_mark
Contributor I
I have posted this in the CodeWarrior forum as well.
 
I am having a difficulty with the R/W on the ColdFire 5484. When I write to a location that falls within one of the address spaces of a FlexBus chip select, the write line goes low and never returns high. From all I can tell the the FBCTL registers and PAR_FBCTL registers are set appropriately. For starters, I have used the M5485 stationary that comes with CodeWarrior and inserted the line:
 
*(uint16 *)0xFE000000 = 0x5555;
 
after the declaration of ch in main.c. The settings of the relevant registers are:
 
PAR_FBCTL = 0x5577
CSAR0 = 0xFE00
CSMR0 = 0x001F0001
CSCR0 = 0x00001980
 
When I first begin debugging M5485 UART SRAM, PPDSDR_FBCTL has the value 0xFD indicating that the R/W line is high. Once I execute the line that writes to 0xFE000000, PPDSDR_FBCTL has the value 0xF8, indicating the R/W line is low and retains that value indefinitely. I have tried the same operation on a board we have developed and have gotten the same result, and I have also used equipment to confirm the status of the R/W line. Is there something that I have overlooked in configuring the chip? FYI, I am using CodeWarrior 5.7.1844 with the P&E Parallel BDM. We use the M548xEVB Lite Board with a MCF5484 and use a MCF5484 on our in house developed board as well. 
 
Thanks in advance,
mr_mark
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mnorman
NXP Employee
NXP Employee

Between bus cycles, the R/W* line will continue to be driven in it's previous state until the next bus cycle in which it needs to be changed.

-mnorman

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mr_mark
Contributor I

Thanks for the reply mnorman. That makes sense, I just never came across anything that identified explicitly as to how it operated.

Thanks again,

mr_mark 

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