Can't get MC68360 SCC working in transparent mode

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Can't get MC68360 SCC working in transparent mode

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Contributor II

What I'm trying to achive is have a base pattern running when nothing else is transmitting and when I want to transmit data, it should be sent and then return to the base pattern.

I've set up two TxBD's, the first one with R and CM flag set and a second one with W flag set to be enabled with R flag later. What I can see happen is that the first TxBD is started and when I later set the R flag for the second, that one is started and when finished the first one is started again. However when I try to start the second one once more, it won't start.

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Contributor II

Hi Mike

Thanks for your suggestions.

 

I got it to work by:

 

  1. setting R, CM, W on both BDs
  2. BD1 is now running
  3. At a later point in time: Clear W on BD1
  4. Now BD2 is running
  5. Set W on BD1 again
  6. After BD2 finished, BD1 is now running

 

I can repeat this sequence many times.

 

/Kenneth

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Contributor II

Sorry, I forgot to mention that in step 7 above, R bit is set to trigger the start of transmission of second BD but it is not.

Also after som more investigation it seems that the R bit was never cleared from the first transmission as I would have expected.

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NXP TechSupport
NXP TechSupport

Hello Kenneth,

There with below added info at <MC68360UMAD.pdf> about SCC initialization:

pastedImage_1.png

It looks like the second BD R bit is not cleared automatically.

Could you manually clear R bit of second BD after Step 6? If that could make the second BD excute again?


Have a great day,
Mike

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Contributor II

Hi Mike

Thanks for your suggestions.

 

I got it to work by:

 

  1. setting R, CM, W on both BDs
  2. BD1 is now running
  3. At a later point in time: Clear W on BD1
  4. Now BD2 is running
  5. Set W on BD1 again
  6. After BD2 finished, BD1 is now running

 

I can repeat this sequence many times.

 

/Kenneth

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NXP TechSupport
NXP TechSupport

Hi Kenneth,

Thanks for the info.

Nice to hear the issue was fixed.

B.R.

Mike

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Contributor II

Hi Mike

SCCE was cleared before starting the sequence and at the time of starting BD2, TX bit was set indicating an underrun but clearing the bit would not start BD2. Also the question is if it should matter, My understanding is that when encountering a BD with R = zero then this BD should be skipped (or possible wait until set) and continue to next BD which seems to happen the first round.

Kenneth

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Contributor II

Hi Mike

Thanks for your reply, but my interpretation is that when the CP encounters a BD with the CM bit set it doesn't clear the R bit after execution instead of clearing it as normal, nothing more and this. The sequence when running my configuration is as follows:

1. First BD is set with flags R and CM

2. Second BD is set with W (W = last BD)

3. At this point only first BD is running continously

4. Second BD is set with R (W still set)

5. Second BD is executing

6. First BD is executing

7. Second is not started again

So it seems it works once but no more.

/Kenneth

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NXP TechSupport
NXP TechSupport

Hi,

To be honest, I have no experience about MC68360 SCC module.

I read the MC68360 user manual chapter 7.10.6 SCC Buffer Descriptors with below description:

The CP processes the Tx BDs in a straightforward fashion. Once the transmit side of an
SCC is enabled, it starts with the first BD in that SCC’s transmit table. Once the CP detects
that the Tx BD R-bit was set, it will begin processing the buffer. (The CP will detect that the
BD is ready either by polling the R-bit periodically or by the user writing to the transmit-ondemand
register (TODR).) Once the data from the BD has been placed in the transmit FIFO,
the CP moves on to the next BD, again waiting for that BD’s R-bit to be set. Thus, the CP
does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the
CP sees the wrap (W) bit set in a BD, it goes back to the beginning of the BD table after
processing of the BD is complete. After using a BD, the CP normally sets the R-bit to not-ready;

thus, the CP will not use a BD twice until the BD has been confirmed by the CPU32+
core. (The one exception to this rule is that the QUICC supports an option for repeated transmission,
called the continuous mode, whereby the R-bit is left in the ready position. This is
available in some protocols.)

It looks like you set the first TxBD with continous mode (CM flag set).

So the CP will continue to transmit the first TxBD.

Thanks for the attention.

best regards,

Mike

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