54455EVB, FEC dropping every other packet

[SeeUnit]

Hello,

I'm trying to create an Ethernet device driver for the CF54455.  Unfortunately I cant get it to work.

Every incomming Ethernet packet generates an interrupt, and the MIB counters show that the packet has arrived without errors.  No interrupt errors occur, and no errors are present in the buffer descriptors (I have tested that they work separately).

When I check the buffer descriptors (breakpoint in the ISR), the FLAG and LENGTH fields are correctly updated by DMA, and the data pointer is correctly initialised (on boundary etc) and adequate memory is allocated.

The problem is that the packet is only DMA'd into the allocated memory 50% of the time (every other packet).  The buffer descriptor information claims that something should be there, but it isn't!  I've tested this by pre-setting the allocated receive buffer with a data patern, but nothing changes after the DMA.

The FEC was initialised in the same order described in the datasheet.

I'm at a complete loss as to where to look next.

Can anyone help?!

Kind regards

Dave

[TomE]

Nothing in the Errata. I'd suggest:

1 - Search this forum for all references to that part number, for "FEC", "ethernet" and any other keywords you can think of.

2 - Find some working code to copy. if you google for a register definition specific to that ethernet controller type you'll probably find soething.

Tom

[SeeUnit]

Thank you for your reply.

I checked the errata & unsuccessfully searched the forums.  Freescale has sent me some example code, which I copied (without looking at my old code to make sure they are completely different) - the result was the same!!!

I have narrowed down the problem a little further though, in case it jogs anones memories.

It would appear that it isnt dropping every other packet after all, just putting them in the wrong place.

 - The first packet does get dropped.  It exists nowhere in memory (only the first packet, I could live with it).

 - The second packet matches up with the second desciptor - works.

 - The third packet alters the third buffer descriptor flags & length, however updates the FIRST descriptors data buffer.

 - The fourth packet matches the fourth buffer descriptor ok.

 - The fifth packet updates the fifth buffer descriptor, but updates the THIRD buffer descriptor data pointer.

 -  The trend continues

It appears that the EVEN buffer descriptors work, whilst the odd buffer descriptor data pointers are offset by one descriptor.

Does that give any clues?

Kind regards

[TomE]

Do you have the caches enabled or not? If you do, try it with them off.

Do you have the descriptors and buffers all aligned to 128 bits?

Tom

[SeeUnit]

> Do you have the descriptors and buffers all aligned to 128 bits?

I think you may have the answer

The buffers were 128, but the descriptors were aligned to 32.  Changing them to 128 did the job.

The datasheet says "Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned" - so I set them to 32 (because it was easier for testing).  The quote from the datasheet suggests that it should have worked though, so what was I missing?

Thanks for the help!!!!