5208 SDR SDRAM MOVEM.L Instruction Whacks Stack, otherwise SDRAM works

[prenton]

I have my 'A71' board which has 5208 cpu, SDRAM, Flash, etc.
I have 5208 eval pcb, and all works fine there.
I reconfigured the SDRAm for my pcb, and have a problem

I have two 'A71' boards, and problem is identical on both.

movem issues...

using 32-bit bus SDR SDRAM on 5208 
DRAM is :  MT48LC16M16A2TG-7E  ( using two parts to get 32-bits wide)

I have tried various settings for the SDRAM config, no changes by any setting change.

The memory works to run from (running routines from SDRAM), the stack in SDRAM works,
however, the movem instruction does incorrect things which results in whacking the
stack and crashing things...

The incorrect things which are done are very repeatable, so makes me think it is
a config thing.  I wrote a function which I call while walking through single step
in the debugger to see what it does exactly.  I have a pattern in this memory before
I do this, so I can see if anything is touched by the instruction.

- - - - - - -  - - - - -

First, to see what is going where, I set the registers to:

D3 D3D3D3D3
D4 D4D4D4D4
D5 D5D5D5D5 
D6 D6D6D6D6
D7 D7D7D7D7
A3 A3A3A3A3
A4 A4A4A4A4
A5 A5A5A5A5
A6 A6A6A6A6

and do:

movem.l  d3-d7/a3-a6,64(a7) 
  (this was in the dBug printf compilation, which
   was what was crashing )

when stack ptr at 4001ff1C
results are:

1ff50  UNCHANGED UNCHANGED UNCHANGED D3D3D3D3
1FF60  A6A6A6A6 000000000 A6A6A6A6 00000000
1FF70  A3A3A3A3 A4A4A4A4 A5A5A5A5 A6A6A6A6

when should be:

1ff50  UNCHANGED UNCHANGED UNCHANGED D3D3D3D3
1FF60  D4D4D4D4 D5D5D5D5 D6D6D6D6 D7D7D7D7
1FF70  A3A3A3A3 A4A4A4A4 A5A5A5A5 A6A6A6A6

------------------------------------------------------------------------

when stack ptr at 40001ff20
registers same values,

results are:

1ff60  D3D3D3D3 A6A6A6A6 00000000 A6A6A6A6
1FF70  00000000 D7D7D7D7 A3A3A3A3 A4A4A4A4
1FF80  A5A5A5A5 A6A6A6A6 UNCHANGED UNCHANGED  

when should be:

1ff60  D3D3D3D3 D4D4D4D4 D5D5D5D5 D6D6D6D6
1FF70  D7D7D7D7 A3A3A3A3 A4A4A4A4 A5A5A5A5 
1FF80  A6A6A6A6 UNCHANGED UNCHANGED UNCHANGED

-------------------------------------------------------------------------

When stack ptr at 40001ff24
registers same values, 

1ff60  UNCHANGED A5A5A5A5 00000000 A5A5A5A5
1FF70  00000000 D6D6D6D6 D7D7D7D7 A3A3A3A3
1FF80  A4A4A4A4 00000000 00000000 UNCHANGED

when should be:

1ff60  UNCHANGED D3D3D3D3 D4D4D4D4 D5D5D5D5
1FF70  D6D6D6D6 D7D7D7D7 A3A3A3A3 A4A4A4A4
1FF80  A5A5A5A5 A6A6A6A6 UNCHANGED UNCHANGED

-------------------------------------------------------------------------

When stack ptr at 40001ff28
registers same values, 

1ff60  UNCHANGED A4A4A4A4 00000000 A4A4A4A4
1FF70  00000000 D5D5D5D5 D6D6D6D6 D7D7D7D7
1FF80  A3A3A3A3 00000000 00000000 A6A6A6A6

when should be:

1ff60  UNCHANGED UNCHANGED D3D3D3D3 D4D4D4D4 
1FF70  D5D5D5D5 D6D6D6D6 D7D7D7D7 A3A3A3A3
1FF80  A4A4A4A4 A5A5A5A5 A6A6A6A6 UNCHANGED

--------------------------------------------------------------------------

My SDRAM config, in dBug in sysinit.c
values based on recommendations from Freescale by email.

delay before calling a bit.

0xFC0A8110 =0x40000019; at 0x40000000 size is 64 Megs
0xFC0A8114 =0x44000019; at 0x44000000 size is 64 Megs
0xFC0A8008 =0x52211500;
 
0xFC0A800C =0x98F70000;
0xFC0A8004 =0xC1080002;
0xFC0A8000 =0x008D0000;
0xFC0A8004 =0xC1080002;

delay a bit here
 
0xFC0A8004 =0xC1080004; do a refresh 8x
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;
0xFC0A8004 =0xC1080004;

 
delay a bit here 

0xFC0A8000 =0x008D0000;
0xFC0A8004 =0xC1080000;
0xFC0A8004 =0x51080000;
 
delay a bit here

SDRAM now ready to go.

I then run a memory test by putting a pattern in and reading it out (which gives me
my background pattern for the test above, (the memory test always passes).

I have tried slowing things down by changing values in the setup above, but no changes
in the results.

----------------------

SDRAM is connected as follows:
(r33 is 33 ohm resistor pack very small)

CPU      SDRAM

A0  R33 A0
A1  R33 A1
A2  R33 A2
A3  R33 A3
A4  R33 A4
A5  R33 A5
A6  R33 A6
A7  R33 A7
A8  R33 A8
A9  R33 A9
SD_A10  R33 A10
A11  R33 A11
A12  R33 A12

A14  R33 BA0
A15  R33 BA1

SD_CKE  R33 CKE
SD_CLK  R33 CLK
SD_CS0  R33 CS
SD_WE  R33 WE
SD_CAS  R33 CAS
SD_RAS  R33 RAS

one SDRAM has
D16-D31  R33 DQ0-DQ15
SD_DQMN_3 R33 DQMH
SD_DQMN_2 R33 DQML

and the other has
D0-D15  R33 DQ0-DQ15
SD_DQMN_1 R33 DQMH
SD_DQMN_0 R33 DQML

then,
SD_DR_DQS loop to memory and back to SD_DQS2 and SD_DQS3
------------------------------------------------------------------------------------------

[prenton]

yes, I changed it yesterday to 4 and it worked...

Paul

[melissa_hunter]

It looks like your initialization sequence isn't quite right. In particular, for a 32-bit wide memory you should be using a burst length of 4 instead of 8.

Here is the init sequence we are using for one of our 532x boards that has 32-bit wide SDR on it:

writemem.l 0xFC0B8110 0x40000018  ; SDCS0

writemem.l 0xFC0B8008 0x42222600  ; SDCFG1
writemem.l 0xFC0B800C 0x54730000  ; SDCFG2

; Issue PALL
writemem.l 0xFC0B8004 0xC0130002  ; SDCR

; Perform two refresh cycles
writemem.l 0xFC0B8004 0xC0130004  ; SDCR
writemem.l 0xFC0B8004 0xC0130004  ; SDCR

; Write mode register
writemem.l 0xFC0B8000 0x00890000  ; SDMR

; Lock SDMR
writemem.l 0xFC0B8004 0x40130000  ; SDCR

; Enable refresh
writemem.l 0xFC0B8004 0x50130000  ; SDCR

; Wait a bit
delay 100

It's a different product, but it uses the same SDRAMC as the 5208. So you should be able to follow this init sequence. You'll need to modify the mux value for the SDRAM you are using and you might need a few tweaks to the timing values as well, but I think this should be a good starting point for you.

Hope this helps,

Melissa

[adam07]

In the last command as as the dqs signals are externally shorted and routed to a DQS as it is shown in the AN2982.pdf for 32 bit SDR-SDRAM, the las should be:

; ENABLE SDMR
writemem.l 0xFC0A8004 0x50144000  ; SDCR

am I correct?