debug and program flash and DDR validation are hanging because of the Debug2 [30] register.

[Em31]

We have a custom board that runs LS1046ardb chip on it. Currently, we are witnessing a lot of capabilities on the codewarrior that is stuck because the DEBUG_2 [30]  (0x01080F04) was never set.

Below is the piece of code that is stuck in the hardware initialization file. We could not find the register DEBUG_2 in any documentation. Could we get some insight into what it is trying to do, why, and what may cause the chip to get stuck at this stage?

void A009803_Erratum(void)

{

volatile uint32_t * debug2 = (uint32_t *)DEBUG_2_ADDR;

   // 1. Configure the DDR registers as normal with parity enabled

   WRITE32(DDRmc1_SDRAM_CFG_2_ADDR, (DDRmc1_SDRAM_CFG_2_VAL | 0x20));

   // 2. Set ERR_DIS[APED]: 1b - Address parity errors are not detected or reported.

   WRITE32(DDRmc1_ERR_DISABLE_ADDR, DDRmc1_ERR_DISABLE_VAL | 0x100);

   // 3. Set DDR_SDRAM_CFG[MEM_EN]

   WRITE32(DDRmc1_SDRAM_CFG_ADDR, (DDRmc1_SDRAM_CFG_VAL | SDRAM_CFG_MEM_EN_MASK));

   // 4. Poll for DEBUG_2[30] to be set

   while ((*debug2 & 0x02000000) == 0) {}

   // 5. Clear ERR_DIS[APED]. Parity checking is now enabled

   WRITE32(DDRmc1_ERR_DISABLE_ADDR, DDRmc1_ERR_DISABLE_VAL & (~0x100));

}

[yipingwang]

Please refer to the following code in ATF source code.

#ifdef ERRATA_DDR_A009803
/* Part 2 of 2 */
if (regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) {
timeout = 400;
do {
mdelay(1);
} while (timeout-- > 0 && !(ddr_in32(&ddr->debug[1]) & 0x2));

if (regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) {
for (i = 0; i < DDRC_NUM_CS; i++) {
if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
continue;
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
MD_CNTL_MD_EN |
MD_CNTL_CS_SEL(i) |
0x070000ed,
MD_CNTL_MD_EN);
udelay(1);
}
}

ddr_out32(&ddr->err_disable,
regs->err_disable & ~DDR_ERR_DISABLE_APED);
}
#endif

[Em31]

During the DDR initial enable of the A009803_Erratum process, the ACE bit of the ERR_DECTECT (0xE40) was triggered.

// 3. Set DDR_SDRAM_CFG[MEM_EN]
WRITE32(DDRmc1_SDRAM_CFG_ADDR, (DDRmc1_SDRAM_CFG_VAL | SDRAM_CFG_MEM_EN_MASK));

Can you explain why and what could cause the ACE bit to be triggered?
Also, we are wondering if ACE bit triggering will prevent the QCVS DDR validation process from being completed.

[Em31]

@yipingwang