Hello Ilya Krasavin,
I explain something about how to use DDRv tool.
If there is SPD on the target board, the user can use reading from SPD method to create and initial QCVS DDR project. If there is no SPD, the user needs to create a default QCVS project, then fill DDR related properties according to DDR data sheet to generate the initial DDR controller configuration parameters.
Then use DDRv tool to connect to the target board to do optimization and validation, the user needs to complete "Centering the clock", "Read ODT and driver" and "Write ODT and dirver" validations to get the final optimized DDR controller configuration parameters.
You could refer to the document "QCVS DDR Tool User Guide" from NXP Semiconductors | Automotive, Security, IoT.
After validation with DDRv in QCVS project, please regenerate DDR configuration script from Project->Generate Processor Expert code, then use DDR controller configuration parameters in script ddrCtrl_1.py in u-boot or DDR initialization file.
If there is SPD on your target, please modify the structure "board_specific_parameters dimm0" in board/freescale/p2041rdb/ddr.c according to the optimized DDR related parameters.
You could refer to this document DDR Controller Configuration on LS2085/LS2080 Bringing up.
If there is no SPD on the target board, you could use raw timing or fixed DDR configuration parameter.
For Raw Timing configuration method, please refer board/freescale/p1023rdb/ddr.c.
For fixed DDR parameters configuration, please refer to board/freescale/corenet_ds/p4080ds_ddr.c
Have a great day,
TIC
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