Question about DDR Validation (Write_Leveling) of LS1012A.

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Question about DDR Validation (Write_Leveling) of LS1012A.

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Contributor I

Hello,

We have a specialist level CW license (CWA-LS-SPLST-NL).
We try to test of DDR_Validation (Write_Leveling) of LS1012A using this license.
However, the LS1012A seems to have no menu for Write_Leveling test.
(In the meantime, we are doing Write_Leveling test with LS1046A.)

Could LS1012A perform Write_Leveling test like LS1046A?

Best Regards,

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NXP TechSupport
NXP TechSupport

Hello Kazuya Yamauchi,

LS1012A uses a different controller compared to other QorIQ devices.

There is no validation selection in QCVS tool. This controller has only one chip select, 16-bit data bus, and fixed 1000MT/s data rating with DDR3L. The one chip select is very lightly loaded system with point to point connection if one x16 DRAM is used. The fixed data rate of 1000MT/s for DDR3L is relatively very slow with much margins in DRAM which are regularly are sold at 1600MT/s rating or higher. there is no clock adjust, clock is fixed at 1/2 clk delay. With one (or max two) DRAM chip the write leveling is not a concern, since there is no write leveling or minimal difference in the address bus (never the less write leveling is done via controller which ensures correct relationship between clock and strobe. we have had very tough time failing this DDR interface after all the calibration that are provided in uboot (also explained in the reference manual) are performed. Customers can manually change the ODT/ driver for both DRAM and controller to obtain best setting, but based what I have observed in my testing the uboot values we have used are optimized values for any board with this controller and this single configuration


Have a great day,
TIC

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NXP TechSupport
NXP TechSupport

Hello Kazuya Yamauchi,

LS1012A uses a different controller compared to other QorIQ devices.

There is no validation selection in QCVS tool. This controller has only one chip select, 16-bit data bus, and fixed 1000MT/s data rating with DDR3L. The one chip select is very lightly loaded system with point to point connection if one x16 DRAM is used. The fixed data rate of 1000MT/s for DDR3L is relatively very slow with much margins in DRAM which are regularly are sold at 1600MT/s rating or higher. there is no clock adjust, clock is fixed at 1/2 clk delay. With one (or max two) DRAM chip the write leveling is not a concern, since there is no write leveling or minimal difference in the address bus (never the less write leveling is done via controller which ensures correct relationship between clock and strobe. we have had very tough time failing this DDR interface after all the calibration that are provided in uboot (also explained in the reference manual) are performed. Customers can manually change the ODT/ driver for both DRAM and controller to obtain best setting, but based what I have observed in my testing the uboot values we have used are optimized values for any board with this controller and this single configuration


Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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