QCVS / Validation of DDR

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QCVS / Validation of DDR

Contributor II

Hi community,

I have a question to validation of DDR. With CodeWarrior for Power Architecture (10.5.1) and activated license for DDR Validation we get a nonsense results. For example following results we got for a test of skews on different memory lanes:


Our configuration:

- T2081

- 64-bit DDR3L + 8-bit ECC

- 933MHz CLK 

With CodeWarrior for ARMv8 and Layerscape LS1046A ist the validation of DRAM ok.

Any ideas, what's wrong?

Thank you very much!

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NXP TechSupport
NXP TechSupport

Hello Radek Raichel,

Please check whether DDR frequency setting configured by RCW is coincident with DDR Properties configuration in QCVS project.

Please check whether you configured DDR Properties parameters according to DDR data sheet.

After DDR validation, please check "Operational DDR tests" to do testing with the latest optimized DDR controller configuration parameters.

Please check whether you use the latest QCVS for PA 4.5 from Help->Install New Software->already installed in CodeWarrior IDE.

Please refer to the document https://community.nxp.com/docs/DOC-333349.

Have a great day,

Note: If this post answers your question, please click the Correct Answer button. Thank you!

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