How to disable DRAM initialization in U-Boot?

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How to disable DRAM initialization in U-Boot?

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Contributor I

I'm working with the T1042 board. By default, DRAM is initialized so that all values read 0xdeadbeef. I want it to instead start up, and have what ever inherent values the DRAM cells happen to be.  Essentially I want to skip the DRAM testing/initialization. How can I do this? I think it might be in arch/powerpc/cpu/mpc85xx/start.S but I'm not to sure how to change it.

I've also tried modifying common/board_f.c where there is a section I can comment out things like dram_init and test_dram but removing these leave me with the following error repeatedly (I'm not even sure if it would be correct to remove these):

Call backtrace: Bad trap at PC: eff4829c, SR: 1000, vector=d00                  
                                          
NIP: EFF4829C XER: 00000000 LR: EFF4828C REGS: fdd00570 TRAP: 0d00 DAR: FFAEDFB8
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00                                 
                                                                                
GPR00: EFF4828C FDD00660 FDD03F20 00000010 00000020 EFFAED84 FDD0061C FFFFFFFE  
GPR08: 00000000 FFAEDFB8 00000020 FDD00660 EFF90E20 24C20000 00000000 7FF6B5D4  
GPR16: 7FF6B5CC 0000000A 00000020 00000000 00001000 FDD006B0 EFFAED98 EFFBCEF0  
GPR24: 00000007 00000000 00000000 00000000 00000000 FDD007B0 EFFC53E4 00000000  
Call backtrace: Bad trap at PC: eff4829c, SR: 1000, vector=d00   

Any solutions?

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NXP TechSupport
NXP TechSupport

> I'm not even sure if it would be correct to remove these

Incorrect.

DDR controller is not initialized in this case.

Which exactly board is in question?

Is ECC used?

Refer to the QorIQ T1040 Reference Manual, Chapter 14 DDR Memory Controller

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Contributor I

The board is the T1042D4RDB. It's possible ECC is on. Maybe disabling that will prevent this error?

I have tried modifying drivers/ddr/fsl/ctrl_regs.c and by looking at chapter 14 of the manual, I would think setting d_init to 0 in set_ddr_sdram_cfg_2(), would give me what I want. Since when this isn't set, ddr_data_init isn't used. But this also results in a similar error. Most of the time it's stuck at:

"DDR Chip-Select Interleaving Mode: CS0+CS1"

But d_init clearly is the data initialization bit. In the same function I see ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; which is 0xdeadbeef. So I know I'm close but I can't see what else I need to set so I don't get an error.

Note: I also tried setting ecc_en to 1 in set_ddr_sdram_cfg() which also didn't help.

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NXP TechSupport
NXP TechSupport

 I would think setting d_init to 0 in set_ddr_sdram_cfg_2(), would give me what I want.

In this case it is required to disable ECC by setting DDR_DDR_SDRAM_CFG[ECC_EN]=0

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Contributor I

I tried this as well amd i still get errors. If i restart the board repeatedly it will eventually start properly, but the memory doesnt look random like i would expect it to. Is there anywhere else in start up that would write to DRAM? 

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NXP TechSupport
NXP TechSupport

Having DDR_SDRAM_CFG[ECC_EN]=0 and DDR_SDRAM_CFG_2[D_INIT]=0 before setting DDR_SDRAM_CFG[MEM_EN]=1 is definitely enough to not initialize the SDRAM contents.

Please use a debugger to check the DDR controller registers settings just before the MEM_EN is set.

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Contributor I

I'll use the debug to look into the rest. But just a interesting thing I noticed, the reference manual says to set mem_en after all other memory configurations have been set. But by default, u-boot sets this first.

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